230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)  macro
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
362 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_enable()
369 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_enable()
407 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_disable()
413 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_disable()
423 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()
433 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()
1630 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1645 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1665 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1682 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1690 	val = pll_readl(XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1701 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1709 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1853 	val_aux = pll_readl(pll->params->aux_reg, pll);  in _clk_plle_tegra_init_parent()
2468 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2485 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2508 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2537 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2545 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()