Lines Matching full:common
163 .common = {
203 .common = {
391 &pll_cpu_clk.common,
392 &pll_audio_base_clk.common,
393 &pll_video_clk.common,
394 &pll_ve_clk.common,
395 &pll_ddr0_clk.common,
396 &pll_periph0_clk.common,
397 &pll_isp_clk.common,
398 &pll_periph1_clk.common,
399 &pll_ddr1_clk.common,
400 &cpu_clk.common,
401 &axi_clk.common,
402 &ahb1_clk.common,
403 &apb1_clk.common,
404 &apb2_clk.common,
405 &ahb2_clk.common,
406 &bus_ce_clk.common,
407 &bus_dma_clk.common,
408 &bus_mmc0_clk.common,
409 &bus_mmc1_clk.common,
410 &bus_mmc2_clk.common,
411 &bus_dram_clk.common,
412 &bus_emac_clk.common,
413 &bus_hstimer_clk.common,
414 &bus_spi0_clk.common,
415 &bus_otg_clk.common,
416 &bus_ehci0_clk.common,
417 &bus_ohci0_clk.common,
418 &bus_ve_clk.common,
419 &bus_tcon0_clk.common,
420 &bus_csi_clk.common,
421 &bus_de_clk.common,
422 &bus_codec_clk.common,
423 &bus_pio_clk.common,
424 &bus_i2s0_clk.common,
425 &bus_i2c0_clk.common,
426 &bus_i2c1_clk.common,
427 &bus_uart0_clk.common,
428 &bus_uart1_clk.common,
429 &bus_uart2_clk.common,
430 &bus_ephy_clk.common,
431 &bus_dbg_clk.common,
432 &mmc0_clk.common,
433 &mmc0_sample_clk.common,
434 &mmc0_output_clk.common,
435 &mmc1_clk.common,
436 &mmc1_sample_clk.common,
437 &mmc1_output_clk.common,
438 &mmc2_clk.common,
439 &mmc2_sample_clk.common,
440 &mmc2_output_clk.common,
441 &ce_clk.common,
442 &spi0_clk.common,
443 &i2s0_clk.common,
444 &usb_phy0_clk.common,
445 &usb_ohci0_clk.common,
446 &dram_clk.common,
447 &dram_ve_clk.common,
448 &dram_csi_clk.common,
449 &dram_ohci_clk.common,
450 &dram_ehci_clk.common,
451 &de_clk.common,
452 &tcon_clk.common,
453 &csi_misc_clk.common,
454 &csi0_mclk_clk.common,
455 &csi1_sclk_clk.common,
456 &csi1_mclk_clk.common,
457 &ve_clk.common,
458 &ac_dig_clk.common,
459 &avs_clk.common,
460 &mbus_clk.common,
461 &mipi_csi_clk.common,
465 &pll_audio_base_clk.common.hw
482 &pll_periph0_clk.common.hw,
487 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
488 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
493 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
494 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
495 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
496 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
498 [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
499 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
500 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
501 [CLK_CPU] = &cpu_clk.common.hw,
502 [CLK_AXI] = &axi_clk.common.hw,
503 [CLK_AHB1] = &ahb1_clk.common.hw,
504 [CLK_APB1] = &apb1_clk.common.hw,
505 [CLK_APB2] = &apb2_clk.common.hw,
506 [CLK_AHB2] = &ahb2_clk.common.hw,
507 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
508 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
509 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
510 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
511 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
512 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
513 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
514 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
515 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
516 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
517 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
518 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
519 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
520 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
521 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
522 [CLK_BUS_DE] = &bus_de_clk.common.hw,
523 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
524 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
525 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
526 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
527 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
528 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
529 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
530 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
531 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
532 [CLK_MMC0] = &mmc0_clk.common.hw,
533 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
534 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
535 [CLK_MMC1] = &mmc1_clk.common.hw,
536 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
537 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
538 [CLK_MMC2] = &mmc2_clk.common.hw,
539 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
540 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
541 [CLK_CE] = &ce_clk.common.hw,
542 [CLK_SPI0] = &spi0_clk.common.hw,
543 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
544 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
545 [CLK_DRAM] = &dram_clk.common.hw,
546 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
547 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
548 [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
549 [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
550 [CLK_DE] = &de_clk.common.hw,
551 [CLK_TCON0] = &tcon_clk.common.hw,
552 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
553 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
554 [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
555 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
556 [CLK_VE] = &ve_clk.common.hw,
557 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
558 [CLK_AVS] = &avs_clk.common.hw,
559 [CLK_MBUS] = &mbus_clk.common.hw,
560 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
567 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
568 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
573 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
574 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
575 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
576 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
578 [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
579 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
580 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
581 [CLK_CPU] = &cpu_clk.common.hw,
582 [CLK_AXI] = &axi_clk.common.hw,
583 [CLK_AHB1] = &ahb1_clk.common.hw,
584 [CLK_APB1] = &apb1_clk.common.hw,
585 [CLK_APB2] = &apb2_clk.common.hw,
586 [CLK_AHB2] = &ahb2_clk.common.hw,
587 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
588 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
589 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
590 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
591 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
592 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
593 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
594 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
595 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
596 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
597 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
598 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
599 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
600 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
601 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
602 [CLK_BUS_DE] = &bus_de_clk.common.hw,
603 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
604 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
605 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
606 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
607 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
608 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
609 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
610 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
611 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
612 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
613 [CLK_MMC0] = &mmc0_clk.common.hw,
614 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
615 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
616 [CLK_MMC1] = &mmc1_clk.common.hw,
617 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
618 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
619 [CLK_MMC2] = &mmc2_clk.common.hw,
620 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
621 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
622 [CLK_CE] = &ce_clk.common.hw,
623 [CLK_SPI0] = &spi0_clk.common.hw,
624 [CLK_I2S0] = &i2s0_clk.common.hw,
625 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
626 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
627 [CLK_DRAM] = &dram_clk.common.hw,
628 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
629 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
630 [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
631 [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
632 [CLK_DE] = &de_clk.common.hw,
633 [CLK_TCON0] = &tcon_clk.common.hw,
634 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
635 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
636 [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
637 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
638 [CLK_VE] = &ve_clk.common.hw,
639 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
640 [CLK_AVS] = &avs_clk.common.hw,
641 [CLK_MBUS] = &mbus_clk.common.hw,
642 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,