Lines Matching +full:0 +full:x17c00000
32 /* Register Offset definitions for CMU_TOP (0x1b240000) */
33 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
34 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
35 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
36 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
37 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
38 #define PLL_CON0_PLL_SHARED0 0x0100
39 #define PLL_CON3_PLL_SHARED0 0x010c
40 #define PLL_CON0_PLL_SHARED1 0x0140
41 #define PLL_CON3_PLL_SHARED1 0x014c
42 #define PLL_CON0_PLL_SHARED2 0x0180
43 #define PLL_CON3_PLL_SHARED2 0x018c
44 #define PLL_CON0_PLL_SHARED3 0x01c0
45 #define PLL_CON3_PLL_SHARED3 0x01cc
46 #define PLL_CON0_PLL_SHARED4 0x0200
47 #define PLL_CON3_PLL_SHARED4 0x020c
50 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
51 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
52 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
53 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
54 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
55 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
56 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
57 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
58 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
59 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
62 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
63 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
64 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
65 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
66 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
67 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
68 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
69 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
70 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
71 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
72 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
73 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
74 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
75 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
76 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
77 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
78 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
79 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
80 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
81 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
82 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
83 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
84 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
85 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
86 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
87 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
88 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
89 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
90 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
91 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
92 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
95 #define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
96 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
97 #define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
98 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
99 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
100 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
101 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
102 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
103 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
104 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
105 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
106 #define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
107 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
108 #define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
109 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
110 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
111 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
112 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
113 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
114 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
115 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
116 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
117 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
118 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
119 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
120 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
121 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
122 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
123 #define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
124 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
125 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
126 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
127 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
128 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
129 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
130 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
131 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
132 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
133 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
135 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
136 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
137 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
138 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
139 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
140 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
141 #define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
142 #define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
143 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
144 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
147 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
148 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
149 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
150 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
151 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
152 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
153 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
154 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
155 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
156 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
157 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
158 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
159 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
160 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
161 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
162 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
163 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
164 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
165 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
166 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
167 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
168 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
169 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
170 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
171 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
172 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
173 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
174 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
175 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
176 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
177 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
178 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
179 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
180 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
181 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
182 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
183 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
184 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
185 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
186 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
187 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
188 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
189 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
190 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
191 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
192 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
193 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
455 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
457 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
461 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
465 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
469 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
471 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
475 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
479 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
483 mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
488 0, 2),
491 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
496 0, 2),
499 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
503 mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
505 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
509 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
513 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
515 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
519 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
521 mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
525 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
528 0, 2),
531 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
535 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
538 0, 2),
541 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
545 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
547 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
552 0, 2),
555 0, 2),
560 0, 2),
564 mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
568 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
570 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
574 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
576 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
580 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
584 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
586 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
590 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
592 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
596 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
602 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
604 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
607 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
609 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
611 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
614 CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
616 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
618 CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
621 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
623 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
627 "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
631 CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
635 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
639 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
641 CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
645 "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
649 "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
653 "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
658 0, 3),
661 0, 3),
666 0, 3),
669 0, 3),
673 "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
675 "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
679 "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
683 "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
685 "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
689 "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
693 "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
695 "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
699 "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
702 0, 3),
705 0, 3),
709 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
711 "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
715 "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
717 "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
721 "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
725 "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
729 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
731 CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
735 "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
739 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
743 "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
745 "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
749 "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
751 "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
755 "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
760 "gout_clkcmu_fsys0_pcie", 1, 4, 0),
767 21, 0, 0),
770 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
772 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
774 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
776 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
779 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
781 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
785 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
789 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
793 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
795 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
800 CLK_IS_CRITICAL, 0),
805 CLK_IS_CRITICAL, 0),
810 21, 0, 0),
815 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
818 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
823 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
826 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
831 21, 0, 0),
834 21, 0, 0),
839 21, 0, 0),
844 21, 0, 0),
847 21, 0, 0),
852 21, 0, 0),
855 21, 0, 0),
860 21, 0, 0),
863 21, 0, 0),
866 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
871 21, 0, 0),
874 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
877 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
881 "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
884 21, 0, 0),
889 21, 0, 0),
892 21, 0, 0),
897 21, 0, 0),
902 21, 0, 0),
906 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
908 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
913 21, CLK_IGNORE_UNUSED, 0),
916 21, CLK_IGNORE_UNUSED, 0),
920 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
925 21, 0, 0),
928 21, 0, 0),
933 21, 0, 0),
936 21, 0, 0),
941 21, CLK_IGNORE_UNUSED, 0),
971 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
972 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600
973 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800
974 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078
975 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080
994 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
1001 0, 0),
1005 0, 0),
1023 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1024 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1025 #define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000
1026 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1027 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000
1028 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004
1029 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008
1050 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1056 CLK_IS_CRITICAL, 0),
1059 CLK_IS_CRITICAL, 0),
1063 CLK_IS_CRITICAL, 0),
1081 /* Register Offset definitions for CMU_FSYS2 (0x17700000) */
1082 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
1083 #define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
1084 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
1086 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
1087 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
1088 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
1089 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
1090 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
1091 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
1093 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
1094 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
1095 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
1096 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
1097 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
1098 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
1099 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
1101 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
1102 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
1103 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
1104 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
1105 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
1106 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
1107 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
1109 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
1110 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
1111 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
1112 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
1113 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
1114 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
1115 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
1117 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
1118 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
1119 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
1120 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
1121 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
1122 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
1179 21, CLK_IGNORE_UNUSED, 0),
1185 21, 0, 0),
1189 21, 0, 0),
1193 21, 0, 0),
1197 21, 0, 0),
1201 21, 0, 0),
1205 21, 0, 0),
1209 21, 0, 0),
1213 21, 0, 0),
1217 21, 0, 0),
1221 21, 0, 0),
1227 21, 0, 0),
1231 21, 0, 0),
1235 21, 0, 0),
1239 21, 0, 0),
1243 21, 0, 0),
1247 21, 0, 0),
1251 21, 0, 0),
1255 21, 0, 0),
1259 21, 0, 0),
1263 21, 0, 0),
1269 21, 0, 0),
1273 21, 0, 0),
1277 21, 0, 0),
1281 21, 0, 0),
1285 21, 0, 0),
1289 21, 0, 0),
1293 21, 0, 0),
1297 21, 0, 0),
1301 21, 0, 0),
1305 21, 0, 0),
1321 /* Register Offset definitions for CMU_FSYS1 (0x17040000) */
1322 #define PLL_LOCKTIME_PLL_MMC 0x0000
1323 #define PLL_CON0_PLL_MMC 0x0100
1324 #define PLL_CON3_PLL_MMC 0x010c
1325 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
1326 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
1327 #define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
1329 #define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
1330 #define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
1332 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
1333 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
1334 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
1336 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
1337 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
1338 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
1339 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
1341 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
1342 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
1343 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
1344 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
1376 0, 1),
1382 CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
1388 21, CLK_IGNORE_UNUSED, 0),
1392 21, CLK_SET_RATE_PARENT, 0),
1396 21, 0, 0),
1400 21, 0, 0),
1404 21, 0, 0),
1408 21, 0, 0),
1412 21, 0, 0),
1416 21, 0, 0),
1420 21, 0, 0),
1424 21, 0, 0),
1428 21, 0, 0),
1448 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1449 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600
1450 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
1451 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
1452 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098
1453 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
1454 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4
1455 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
1487 0, 0),
1491 21, 0, 0),
1495 0, 0),
1499 21, 0, 0),
1515 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1516 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1517 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
1518 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
1519 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
1520 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
1521 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
1522 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
1523 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
1524 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
1525 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
1526 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
1527 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
1528 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
1529 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
1530 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
1531 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
1532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
1533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
1534 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
1535 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
1536 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
1537 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
1538 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
1539 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
1540 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
1541 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
1542 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
1543 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
1544 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
1545 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
1546 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
1547 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
1548 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1549 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1550 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1551 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1552 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1553 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1554 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
1555 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
1612 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1614 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1616 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1618 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1620 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1622 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1625 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1632 0, 4),
1635 0, 4),
1638 0, 4),
1641 0, 4),
1644 0, 4),
1647 0, 4),
1650 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1658 21, 0, 0),
1662 21, 0, 0),
1666 21, 0, 0),
1670 21, 0, 0),
1674 21, 0, 0),
1678 21, 0, 0),
1682 21, 0, 0),
1686 21, 0, 0),
1690 21, 0, 0),
1694 21, 0, 0),
1698 21, 0, 0),
1702 21, 0, 0),
1708 21, 0, 0),
1712 21, 0, 0),
1716 21, 0, 0),
1720 21, 0, 0),
1724 21, 0, 0),
1728 21, 0, 0),
1732 21, 0, 0),
1736 21, 0, 0),
1740 21, 0, 0),
1744 21, 0, 0),
1748 21, 0, 0),
1752 21, 0, 0),
1770 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1771 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1772 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
1773 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
1774 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
1775 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
1776 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
1777 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
1778 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
1779 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
1780 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
1781 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
1782 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
1783 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
1784 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
1785 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
1786 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
1787 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
1788 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
1789 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
1790 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
1791 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
1792 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
1793 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
1794 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
1795 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
1796 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
1797 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
1798 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
1799 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
1800 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
1801 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
1802 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
1803 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
1804 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
1805 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
1806 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
1807 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
1808 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
1809 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
1810 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
1867 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1869 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1871 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1873 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1875 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1877 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1880 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1887 0, 4),
1890 0, 4),
1893 0, 4),
1896 0, 4),
1899 0, 4),
1902 0, 4),
1905 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1913 21, 0, 0),
1917 21, 0, 0),
1921 21, 0, 0),
1925 21, 0, 0),
1929 21, 0, 0),
1933 21, 0, 0),
1937 21, 0, 0),
1941 21, 0, 0),
1945 21, 0, 0),
1949 21, 0, 0),
1953 21, 0, 0),
1957 21, 0, 0),
1963 21, 0, 0),
1967 21, 0, 0),
1971 21, 0, 0),
1975 21, 0, 0),
1979 21, 0, 0),
1983 21, 0, 0),
1987 21, 0, 0),
1991 21, 0, 0),
1995 21, 0, 0),
1999 21, 0, 0),
2003 21, 0, 0),
2007 21, 0, 0),
2025 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2026 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
2027 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058
2028 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c
2029 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060
2050 21, CLK_IGNORE_UNUSED, 0),
2053 21, 0, 0),
2056 21, 0, 0),
2078 return 0; in exynosautov9_cmu_probe()