Lines Matching +full:0 +full:x0600
34 /* Register Offset definitions for CMU_TOP (0x120e0000) */
35 #define PLL_LOCKTIME_PLL_MMC 0x0000
36 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
37 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
38 #define PLL_CON0_PLL_MMC 0x0100
39 #define PLL_CON3_PLL_MMC 0x010c
40 #define PLL_CON0_PLL_SHARED0 0x0140
41 #define PLL_CON3_PLL_SHARED0 0x014c
42 #define PLL_CON0_PLL_SHARED1 0x0180
43 #define PLL_CON3_PLL_SHARED1 0x018c
44 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
45 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
46 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
47 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
48 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
49 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
50 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
51 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
52 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
53 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
54 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
55 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
56 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
57 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
58 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
59 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
60 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
61 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
62 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
63 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
64 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
65 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
66 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
67 #define CLK_CON_DIV_CLKCMU_AUD 0x1810
68 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
69 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
70 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
71 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
72 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
73 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
74 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
75 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
76 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
77 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
78 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
79 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
80 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
81 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
82 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
83 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
84 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
85 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
86 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
87 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
88 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
89 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
90 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
91 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
92 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
93 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
94 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
95 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
96 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
97 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
98 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
99 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
100 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
101 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
102 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
103 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
104 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
105 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
106 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
107 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
108 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
109 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
110 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
111 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
112 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
113 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
114 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
115 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
287 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
291 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
295 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
297 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
299 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
301 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
305 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
309 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
313 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
315 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
317 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
321 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
323 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
325 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
327 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
331 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
333 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
335 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
337 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
341 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
343 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
345 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
351 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
353 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
355 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
357 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
359 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
361 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
365 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
369 CLK_CON_DIV_CLKCMU_AUD, 0, 4),
373 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
375 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
377 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
379 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
383 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
387 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
391 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
393 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
395 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
399 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
401 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
403 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
405 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
409 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
411 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
413 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
415 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
419 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
421 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
423 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
429 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
431 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
433 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
435 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
439 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
443 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
447 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
451 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
455 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
457 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
459 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
464 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
466 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
468 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
470 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
475 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
477 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
479 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
481 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
485 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
487 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
489 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
517 /* Register Offset definitions for CMU_APM (0x11800000) */
518 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
519 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
520 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
521 #define PLL_CON0_MUX_DLL_USER 0x0630
522 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
523 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
524 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
525 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
526 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
527 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
528 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
529 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
530 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
531 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
532 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
533 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
534 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
535 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
536 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
537 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
573 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
574 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
575 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
576 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
589 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
591 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
593 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
599 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
601 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
603 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
608 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
611 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
613 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
615 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
617 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
619 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
621 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
625 0),
627 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
629 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
649 #define PLL_LOCKTIME_PLL_AUD 0x0000
650 #define PLL_CON0_PLL_AUD 0x0100
651 #define PLL_CON3_PLL_AUD 0x010c
652 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
653 #define PLL_CON0_MUX_TICK_USB_USER 0x0610
654 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
655 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
656 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
657 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
658 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
659 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
660 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
661 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
662 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
663 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
664 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
665 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
666 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
667 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
668 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
669 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
670 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
671 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
672 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
673 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
674 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
675 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
676 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
677 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
678 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
679 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
680 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
681 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
682 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
683 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
684 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
685 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
686 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
687 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
688 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
689 #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
690 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
691 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
692 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
693 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
694 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
695 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
696 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
697 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
698 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
699 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
700 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
701 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
702 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
786 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
787 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
788 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
789 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
790 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
791 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
792 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
793 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
805 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
807 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
809 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
811 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
813 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
815 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
817 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
819 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
821 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
823 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
828 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
830 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
832 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
834 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
836 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
839 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
841 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
843 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
845 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
847 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
849 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
851 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
853 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
855 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
857 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
859 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
861 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
867 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
869 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
871 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
873 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
876 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
878 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
880 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
882 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
884 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
886 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
888 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
890 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
892 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
894 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
896 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
898 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
900 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
902 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
904 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
906 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
908 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
910 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
932 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
933 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
934 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
935 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
936 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
937 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
938 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
939 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
940 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
941 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
942 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
943 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
944 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
945 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
946 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
971 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
976 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
978 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
980 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
985 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
987 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
989 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
995 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
998 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
1002 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1004 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
1007 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
1009 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
1012 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
1015 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
1035 /* Register Offset definitions for CMU_G3D (0x11400000) */
1036 #define PLL_LOCKTIME_PLL_G3D 0x0000
1037 #define PLL_CON0_PLL_G3D 0x0100
1038 #define PLL_CON3_PLL_G3D 0x010c
1039 #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
1040 #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
1041 #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
1042 #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
1043 #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
1044 #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
1045 #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
1046 #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
1047 #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
1048 #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
1087 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
1092 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
1098 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1100 CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
1102 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
1105 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
1107 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
1109 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
1111 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
1131 /* Register Offset definitions for CMU_HSI (0x13400000) */
1132 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
1133 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
1134 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
1135 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
1136 #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
1137 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
1138 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
1139 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
1140 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
1141 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
1142 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
1143 #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
1144 #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
1145 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
1146 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
1147 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
1179 4, 1, CLK_SET_RATE_PARENT, 0),
1184 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1191 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1193 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1195 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1197 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1200 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1202 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1205 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1207 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
1209 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
1212 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1214 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1217 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1233 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1234 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1235 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1236 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1237 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1238 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1239 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1240 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1241 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1242 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1243 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1244 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1245 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1246 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1247 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1248 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1249 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1250 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1251 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1252 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1253 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1254 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1255 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1302 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1308 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1310 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1312 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1314 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1316 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1319 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1321 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1323 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1325 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1327 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1329 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1332 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1334 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1337 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1339 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1342 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1345 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1347 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1365 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1366 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1367 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1368 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1369 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1370 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1371 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1372 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1373 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1374 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1375 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1376 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1377 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1378 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1379 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1422 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1429 21, CLK_IGNORE_UNUSED, 0),
1432 21, 0, 0),
1435 21, 0, 0),
1438 21, 0, 0),
1441 21, 0, 0),
1444 21, 0, 0),
1447 21, 0, 0),
1450 21, 0, 0),
1453 21, 0, 0),
1456 21, 0, 0),
1474 /* Register Offset definitions for CMU_PERI (0x10030000) */
1475 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
1476 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
1477 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
1478 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
1479 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
1480 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
1481 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
1482 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
1483 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
1484 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
1485 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
1486 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
1487 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
1488 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
1489 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
1490 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
1491 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
1492 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
1493 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
1494 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
1495 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
1496 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
1497 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
1498 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
1499 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
1500 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
1501 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
1502 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
1503 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
1504 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
1505 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
1506 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
1507 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
1508 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
1566 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
1568 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
1570 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
1572 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
1577 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
1579 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
1581 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
1583 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
1585 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
1587 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
1589 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
1591 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
1593 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
1595 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
1597 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
1599 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
1601 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
1603 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
1605 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
1607 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
1609 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
1612 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
1614 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
1616 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
1619 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
1621 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
1623 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
1625 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
1627 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
1631 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1658 /* Register Offset definitions for CMU_CORE (0x12000000) */
1659 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1660 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
1661 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
1662 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
1663 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
1664 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1665 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
1666 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
1667 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
1668 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
1669 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
1670 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
1671 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
1672 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
1705 4, 1, CLK_SET_RATE_PARENT, 0),
1709 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
1714 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
1720 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
1723 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
1725 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
1728 21, CLK_SET_RATE_PARENT, 0),
1730 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
1732 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
1735 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1738 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
1756 /* Register Offset definitions for CMU_DPU (0x13000000) */
1757 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
1758 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
1759 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
1760 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
1761 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
1762 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
1763 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
1764 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
1765 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
1766 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
1791 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
1798 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1800 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
1802 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
1804 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
1806 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
1808 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
1810 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
1812 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
1838 return 0; in exynos850_cmu_probe()