Lines Matching refs:MUX
89 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
91 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
93 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
95 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
97 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
99 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
101 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
103 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
106 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
108 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
111 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
113 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
114 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
275 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
277 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
279 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
281 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
283 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
286 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
288 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
290 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
292 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
295 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
296 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
298 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
299 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
300 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
302 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
303 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
305 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
306 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
307 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
308 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
309 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
310 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
311 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
455 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
457 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
459 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
461 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
464 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
466 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
468 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
470 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
473 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
474 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
476 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
478 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
479 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
482 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
484 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
487 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
488 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
489 MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
602 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
645 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
647 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
723 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
736 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
738 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
740 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
839 MUX(0, "mout_aclk_peris_66_user",
915 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
918 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
920 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
923 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
926 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
1032 MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
1034 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
1036 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
1039 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
1041 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
1043 MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
1046 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
1048 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
1050 MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
1132 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
1253 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1254 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1255 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),