Lines Matching +full:0 +full:x40c
19 #define RZV2M_SAMPLL4_CLK1 0x104
20 #define RZV2M_SAMPLL4_CLK2 0x108
24 #define DIV_A DDIV_PACK(0x200, 0, 3)
25 #define DIV_B DDIV_PACK(0x204, 0, 2)
26 #define DIV_D DDIV_PACK(0x204, 4, 2)
27 #define DIV_E DDIV_PACK(0x204, 8, 1)
28 #define DIV_W DDIV_PACK(0x328, 0, 3)
30 #define SEL_B SEL_PLL_PACK(0x214, 0, 1)
31 #define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1)
32 #define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1)
33 #define SEL_D SEL_PLL_PACK(0x214, 1, 1)
34 #define SEL_E SEL_PLL_PACK(0x214, 2, 1)
35 #define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
36 #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
40 LAST_DT_CORE_CLK = 0,
76 {0, 1},
83 {0, 0},
87 {0, 1},
91 {0, 0},
95 {0, 1},
98 {0, 0},
103 {0, 6},
110 {0, 0},
155 DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
156 DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
157 DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0),
158 DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1),
159 DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2),
160 DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3),
161 DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4),
162 DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5),
163 DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6),
164 DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7),
165 DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8),
166 DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9),
167 DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10),
168 DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11),
169 DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
170 DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
171 DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
172 DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4),
173 DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5),
174 DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6),
175 DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
176 DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
177 DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0),
178 DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4),
179 DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5),
180 DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6),
181 DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7),
182 DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8),
183 DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9),
184 DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10),
185 DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11),
186 DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12),
187 DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0),
188 DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4),
189 DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5),
190 DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6),
191 DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7),
192 DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8),
193 DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9),
194 DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10),
195 DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11),
196 DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
197 DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
198 DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0),
199 DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4),
200 DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5),
201 DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6),
202 DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7),
203 DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
204 DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
205 DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
206 DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0),
207 DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1),
208 DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
209 DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
210 DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8),
211 DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12),
212 DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
216 DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
217 DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6),
218 DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7),
219 DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8),
220 DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7),
221 DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8),
222 DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9),
223 DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10),
224 DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
225 DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
226 DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
227 DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2),
228 DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23),
229 DEF_RST_MON(R9A09G011_CSI_GPG_PRESETN, 0x614, 6, 22),
230 DEF_RST_MON(R9A09G011_CSI_GPH_PRESETN, 0x614, 7, 23),
231 DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
232 DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9),
233 DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),