Lines Matching +full:0 +full:x584
70 {0, 1},
74 {0, 0},
78 {0, 1},
83 {0, 0},
87 {0, 16},
91 {0, 0},
104 struct cpg_core_clk drp[0];
114 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
187 struct rzg2l_mod_clk drp[0];
192 0x514, 0),
194 0x518, 0),
196 0x518, 1),
198 0x52c, 0),
200 0x52c, 1),
202 0x534, 0),
204 0x534, 1),
206 0x534, 2),
208 0x538, 0),
210 0x540, 0),
212 0x544, 0),
214 0x544, 1),
216 0x544, 2),
218 0x544, 3),
220 0x548, 0),
222 0x548, 1),
224 0x548, 2),
226 0x548, 3),
228 0x550, 0),
230 0x550, 1),
232 0x554, 0),
234 0x554, 1),
236 0x554, 2),
238 0x554, 3),
240 0x554, 4),
242 0x554, 5),
244 0x554, 6),
246 0x554, 7),
248 0x558, 0),
250 0x558, 1),
252 0x558, 2),
254 0x564, 0),
256 0x564, 1),
258 0x564, 2),
260 0x564, 3),
262 0x568, 0),
264 0x568, 1),
266 0x568, 2),
268 0x568, 3),
270 0x568, 4),
272 0x568, 5),
274 0x56c, 0),
276 0x56c, 0),
278 0x56c, 1),
280 0x570, 0),
282 0x570, 1),
284 0x570, 2),
286 0x570, 3),
288 0x570, 4),
290 0x570, 5),
292 0x570, 6),
294 0x570, 7),
296 0x578, 0),
298 0x578, 1),
300 0x578, 2),
302 0x578, 3),
304 0x57c, 0),
306 0x57c, 0),
308 0x57c, 1),
310 0x57c, 1),
312 0x580, 0),
314 0x580, 1),
316 0x580, 2),
318 0x580, 3),
320 0x584, 0),
322 0x584, 1),
324 0x584, 2),
326 0x584, 3),
328 0x584, 4),
330 0x588, 0),
332 0x588, 1),
334 0x590, 0),
336 0x590, 1),
338 0x590, 2),
340 0x594, 0),
342 0x598, 0),
344 0x5a8, 0),
346 0x5a8, 1),
348 0x5ac, 0),
357 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
358 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
359 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
360 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
361 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
362 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
363 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
364 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
365 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
366 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
367 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
368 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
369 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
370 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
371 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
372 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
373 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
374 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
375 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
376 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
377 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
378 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
379 DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
380 DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
381 DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
382 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
383 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
384 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
385 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
386 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
387 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
388 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
389 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
390 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
391 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
392 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
393 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
394 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
395 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
396 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
397 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
398 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
399 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
400 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
401 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
402 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
403 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
404 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
405 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
406 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
407 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
408 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
409 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
410 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
411 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
412 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
413 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
414 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
415 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
416 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
417 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),