Lines Matching refs:DEF_MOD
131 DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
132 DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
133 DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
134 DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
135 DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
136 DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
137 DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
138 DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
139 DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
140 DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
141 DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO),
142 DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO),
143 DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO),
144 DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
145 DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
146 DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
147 DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4),
148 DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4),
149 DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4),
150 DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4),
151 DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
152 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
153 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
154 DEF_MOD("tmu0", 713, R8A779F0_CLK_SASYNCRT),
155 DEF_MOD("tmu1", 714, R8A779F0_CLK_SASYNCPERD2),
156 DEF_MOD("tmu2", 715, R8A779F0_CLK_SASYNCPERD2),
157 DEF_MOD("tmu3", 716, R8A779F0_CLK_SASYNCPERD2),
158 DEF_MOD("tmu4", 717, R8A779F0_CLK_SASYNCPERD2),
159 DEF_MOD("wdt", 907, R8A779F0_CLK_R),
160 DEF_MOD("cmt0", 910, R8A779F0_CLK_R),
161 DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
162 DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
163 DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
164 DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
165 DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
166 DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
167 DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
168 DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),