Lines Matching +full:0 +full:x96
81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
104 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
105 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
106 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
107 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
108 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
109 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
110 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
111 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
121 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
122 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
123 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
124 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
304 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
305 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
306 * 0 0 1 0 Prohibited setting
307 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
308 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
309 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
310 * 0 1 1 0 Prohibited setting
311 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
312 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
313 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
314 * 1 0 1 0 Prohibited setting
315 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
316 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
317 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
318 * 1 1 1 0 Prohibited setting
330 { 0, /* Prohibited setting */ },
334 { 0, /* Prohibited setting */ },
338 { 0, /* Prohibited setting */ },
342 { 0, /* Prohibited setting */ },
372 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); in r8a7795_cpg_mssr_init()