Lines Matching refs:LPC1XX_CGU_BASE_CLK
203 #define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \ macro
220 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
221 LPC1XX_CGU_BASE_CLK(USB0, base_usb0_src_ids, 0),
222 LPC1XX_CGU_BASE_CLK(PERIPH, base_common_src_ids, 0),
223 LPC1XX_CGU_BASE_CLK(USB1, base_all_src_ids, 0),
224 LPC1XX_CGU_BASE_CLK(CPU, base_common_src_ids, 0),
225 LPC1XX_CGU_BASE_CLK(SPIFI, base_common_src_ids, 0),
226 LPC1XX_CGU_BASE_CLK(SPI, base_common_src_ids, 0),
227 LPC1XX_CGU_BASE_CLK(PHY_RX, base_common_src_ids, 0),
228 LPC1XX_CGU_BASE_CLK(PHY_TX, base_common_src_ids, 0),
229 LPC1XX_CGU_BASE_CLK(APB1, base_common_src_ids, 0),
230 LPC1XX_CGU_BASE_CLK(APB3, base_common_src_ids, 0),
231 LPC1XX_CGU_BASE_CLK(LCD, base_common_src_ids, 0),
232 LPC1XX_CGU_BASE_CLK(ADCHS, base_common_src_ids, 0),
233 LPC1XX_CGU_BASE_CLK(SDIO, base_common_src_ids, 0),
234 LPC1XX_CGU_BASE_CLK(SSP0, base_common_src_ids, 0),
235 LPC1XX_CGU_BASE_CLK(SSP1, base_common_src_ids, 0),
236 LPC1XX_CGU_BASE_CLK(UART0, base_common_src_ids, 0),
237 LPC1XX_CGU_BASE_CLK(UART1, base_common_src_ids, 0),
238 LPC1XX_CGU_BASE_CLK(UART2, base_common_src_ids, 0),
239 LPC1XX_CGU_BASE_CLK(UART3, base_common_src_ids, 0),
240 LPC1XX_CGU_BASE_CLK(OUT, base_all_src_ids, 0),
245 LPC1XX_CGU_BASE_CLK(AUDIO, base_common_src_ids, 0),
246 LPC1XX_CGU_BASE_CLK(CGU_OUT0, base_all_src_ids, 0),
247 LPC1XX_CGU_BASE_CLK(CGU_OUT1, base_all_src_ids, 0),