Lines Matching refs:DIV_SEL0
30 #define DIV_SEL0 0x4 macro
261 PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
265 PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
266 PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
267 PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
268 PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
270 static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
304 PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
305 PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
306 PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
699 data->div_sel0 = readl(data->reg + DIV_SEL0); in armada_3700_periph_clock_suspend()
714 writel(data->div_sel0, data->reg + DIV_SEL0); in armada_3700_periph_clock_resume()