Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
20 #include "clk-regmap.h"
21 #include "meson-clkc-utils.h"
22 #include "clk-pll.h"
23 #include "clk-mpll.h"
25 #include <dt-bindings/clock/meson8b-clkc.h>
26 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
60 .data = &(struct meson_clk_pll_data){
63 .shift = 30,
68 .shift = 0,
73 .shift = 9,
78 .shift = 0,
83 .shift = 31,
88 .shift = 29,
98 .index = -1,
105 .data = &(struct clk_regmap_div_data){
107 .shift = 16,
133 .index = -1,
142 * Meson8b and Meson8m2. This doubles the input (or output - it's not clear
176 .data = &(struct meson_clk_pll_data){
179 .shift = 30,
184 .shift = 0,
189 .shift = 10,
194 .shift = 0,
199 .shift = 31,
204 .shift = 29,
223 .data = &(struct clk_regmap_div_data){
225 .shift = 16,
241 .data = &(struct clk_regmap_div_data){
243 .shift = 18,
259 .data = &(struct meson_clk_pll_data){
262 .shift = 30,
267 .shift = 0,
272 .shift = 9,
277 .shift = 31,
282 .shift = 29,
293 .index = -1,
300 .data = &(struct clk_regmap_div_data){
302 .shift = 16,
331 .data = &(struct clk_regmap_gate_data){
359 .data = &(struct clk_regmap_gate_data){
387 .data = &(struct clk_regmap_gate_data){
415 .data = &(struct clk_regmap_gate_data){
443 .data = &(struct clk_regmap_gate_data){
458 .data = &(struct clk_regmap_div_data){
460 .shift = 12,
474 .data = &(struct meson_clk_mpll_data){
477 .shift = 0,
482 .shift = 15,
487 .shift = 16,
492 .shift = 25,
508 .data = &(struct clk_regmap_gate_data){
524 .data = &(struct meson_clk_mpll_data){
527 .shift = 0,
532 .shift = 15,
537 .shift = 16,
553 .data = &(struct clk_regmap_gate_data){
569 .data = &(struct meson_clk_mpll_data){
572 .shift = 0,
577 .shift = 15,
582 .shift = 16,
598 .data = &(struct clk_regmap_gate_data){
615 .data = &(struct clk_regmap_mux_data){
618 .shift = 12,
639 .data = &(struct clk_regmap_div_data){
641 .shift = 0,
655 .data = &(struct clk_regmap_gate_data){
671 .data = &(struct clk_regmap_mux_data){
674 .shift = 0,
680 { .fw_name = "xtal", .name = "xtal", .index = -1, },
730 .data = &(struct clk_regmap_div_data){
732 .shift = 20,
750 .data = &(struct clk_regmap_mux_data){
753 .shift = 2,
776 .data = &(struct clk_regmap_mux_data){
779 .shift = 7,
785 { .fw_name = "xtal", .name = "xtal", .index = -1, },
796 .data = &(struct clk_regmap_mux_data){
799 .shift = 9,
811 { .fw_name = "xtal", .name = "xtal", .index = -1, },
819 .data = &(struct clk_regmap_div_data){
821 .shift = 0,
837 .data = &(struct clk_regmap_gate_data){
945 .data = &(struct clk_regmap_mux_data){
948 .shift = 3,
968 .data = &(struct clk_regmap_gate_data){
985 .data = &(struct clk_regmap_mux_data){
988 .shift = 6,
1007 .data = &(struct clk_regmap_gate_data){
1025 .data = &(struct clk_regmap_mux_data){
1028 .shift = 9,
1048 .data = &(struct clk_regmap_gate_data){
1065 .data = &(struct clk_regmap_mux_data){
1068 .shift = 12,
1087 .data = &(struct clk_regmap_gate_data){
1105 .data = &(struct clk_regmap_gate_data){
1121 .data = &(struct clk_regmap_mux_data){
1124 .shift = 15,
1144 .data = &(struct clk_regmap_gate_data){
1160 .data = &(struct clk_regmap_div_data){
1162 .shift = 4,
1177 .data = &(struct clk_regmap_div_data){
1179 .shift = 12,
1194 .data = &(struct clk_regmap_mux_data){
1197 .shift = 8,
1213 .data = &(struct clk_regmap_div_data){
1215 .shift = 0,
1240 .data = &(struct clk_regmap_mux_data){
1243 .shift = 16,
1255 .data = &(struct clk_regmap_gate_data){
1271 .data = &(struct clk_regmap_gate_data){
1287 .data = &(struct clk_regmap_gate_data){
1317 .data = &(struct clk_regmap_gate_data){
1347 .data = &(struct clk_regmap_gate_data){
1377 .data = &(struct clk_regmap_gate_data){
1407 .data = &(struct clk_regmap_gate_data){
1423 .data = &(struct clk_regmap_mux_data){
1426 .shift = 16,
1438 .data = &(struct clk_regmap_gate_data){
1454 .data = &(struct clk_regmap_gate_data){
1470 .data = &(struct clk_regmap_gate_data){
1500 .data = &(struct clk_regmap_gate_data){
1530 .data = &(struct clk_regmap_gate_data){
1560 .data = &(struct clk_regmap_gate_data){
1590 .data = &(struct clk_regmap_gate_data){
1614 .data = &(struct clk_regmap_mux_data){
1617 .shift = 20,
1629 .data = &(struct clk_regmap_gate_data){
1645 .data = &(struct clk_regmap_mux_data){
1648 .shift = 24,
1660 .data = &(struct clk_regmap_gate_data){
1676 .data = &(struct clk_regmap_mux_data){
1679 .shift = 28,
1691 .data = &(struct clk_regmap_gate_data){
1707 .data = &(struct clk_regmap_mux_data){
1710 .shift = 16,
1722 .data = &(struct clk_regmap_gate_data){
1746 .data = &(struct clk_regmap_mux_data){
1749 .shift = 12,
1761 .data = &(struct clk_regmap_gate_data){
1777 .data = &(struct clk_regmap_mux_data){
1780 .shift = 28,
1792 .data = &(struct clk_regmap_gate_data){
1808 .data = &(struct clk_regmap_mux_data){
1811 .shift = 9,
1821 .index = -1,
1829 .data = &(struct clk_regmap_div_data){
1831 .shift = 0,
1846 .data = &(struct clk_regmap_gate_data){
1863 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1864 * actually manage this glitch-free mux because it does top-to-bottom
1867 * Meson8 only has mali_0 and no glitch-free mux.
1870 { .fw_name = "xtal", .name = "xtal", .index = -1, },
1882 .data = &(struct clk_regmap_mux_data){
1885 .shift = 9,
1904 .data = &(struct clk_regmap_div_data){
1906 .shift = 0,
1921 .data = &(struct clk_regmap_gate_data){
1937 .data = &(struct clk_regmap_mux_data){
1940 .shift = 25,
1959 .data = &(struct clk_regmap_div_data){
1961 .shift = 16,
1976 .data = &(struct clk_regmap_gate_data){
1992 .data = &(struct clk_regmap_mux_data){
1995 .shift = 31,
2022 .data = &(struct meson_clk_pll_data){
2025 .shift = 30,
2030 .shift = 0,
2035 .shift = 9,
2040 .shift = 31,
2045 .shift = 29,
2058 .index = -1,
2065 .data = &(struct clk_regmap_div_data){
2067 .shift = 16,
2097 .data = &(struct clk_regmap_mux_data){
2100 .shift = 9,
2112 .data = &(struct clk_regmap_mux_data){
2115 .shift = 9,
2127 .data = &(struct clk_regmap_div_data){
2129 .shift = 0,
2144 .index = -1,
2152 .data = &(struct clk_regmap_gate_data){
2168 .data = &(struct clk_regmap_mux_data){
2171 .shift = 25,
2183 .data = &(struct clk_regmap_mux_data){
2186 .shift = 25,
2198 .data = &(struct clk_regmap_div_data){
2200 .shift = 16,
2215 .index = -1,
2223 .data = &(struct clk_regmap_gate_data){
2240 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2241 * actually manage this glitch-free mux because it does top-to-bottom
2244 * Meson8 only has vpu_0 and no glitch-free mux.
2247 .data = &(struct clk_regmap_mux_data){
2250 .shift = 31,
2274 .data = &(struct clk_regmap_mux_data){
2277 .shift = 9,
2290 .data = &(struct clk_regmap_div_data){
2292 .shift = 0,
2308 .data = &(struct clk_regmap_gate_data){
2324 .data = &(struct clk_regmap_div_data){
2326 .shift = 0,
2342 .data = &(struct clk_regmap_gate_data){
2358 .data = &(struct clk_regmap_mux_data){
2361 .shift = 15,
2377 .data = &(struct clk_regmap_mux_data){
2380 .shift = 25,
2393 .data = &(struct clk_regmap_div_data){
2395 .shift = 16,
2411 .data = &(struct clk_regmap_gate_data){
2427 .data = &(struct clk_regmap_mux_data){
2430 .shift = 9,
2443 .data = &(struct clk_regmap_div_data){
2445 .shift = 0,
2461 .data = &(struct clk_regmap_gate_data){
2477 .data = &(struct clk_regmap_mux_data){
2480 .shift = 25,
2493 .data = &(struct clk_regmap_div_data){
2495 .shift = 16,
2511 .data = &(struct clk_regmap_gate_data){
2527 .data = &(struct clk_regmap_mux_data){
2530 .shift = 31,
2555 .data = &(struct clk_regmap_mux_data){
2558 .shift = 9,
2571 .data = &(struct clk_regmap_div_data) {
2573 .shift = 0,
2589 .data = &(struct clk_regmap_gate_data){
2614 .data = &(struct clk_regmap_mux_data){
2617 .shift = 25,
2630 .data = &(struct clk_regmap_div_data){
2632 .shift = 16,
2648 .data = &(struct clk_regmap_gate_data){
2664 .data = &(struct clk_regmap_mux_data){
2667 .shift = 27,
2678 * The parent is specific to origin of the audio data. Let the
3708 return -EINVAL; in meson8b_clk_reset_update()
3712 if (assert != reset->active_low) in meson8b_clk_reset_update()
3713 value = BIT(reset->bit_idx); in meson8b_clk_reset_update()
3717 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, in meson8b_clk_reset_update()
3718 BIT(reset->bit_idx), value); in meson8b_clk_reset_update()
3748 unsigned long event, void *data) in meson8b_cpu_clk_notifier_cb() argument
3758 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); in meson8b_cpu_clk_notifier_cb()
3763 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); in meson8b_cpu_clk_notifier_cb()
3770 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); in meson8b_cpu_clk_notifier_cb()
3812 pr_err("failed to get HHI regmap - Trying obsolete regs\n"); in meson8b_clkc_init_common()
3821 rstc->regmap = map; in meson8b_clkc_init_common()
3822 rstc->reset.ops = &meson8b_clk_reset_ops; in meson8b_clkc_init_common()
3823 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); in meson8b_clkc_init_common()
3824 rstc->reset.of_node = np; in meson8b_clkc_init_common()
3825 ret = reset_controller_register(&rstc->reset); in meson8b_clkc_init_common()
3834 meson8b_clk_regmaps[i]->map = map; in meson8b_clkc_init_common()
3840 for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) { in meson8b_clkc_init_common()
3842 if (!hw_clks->hws[i]) in meson8b_clkc_init_common()
3845 ret = of_clk_hw_register(np, hw_clks->hws[i]); in meson8b_clkc_init_common()
3850 meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK]; in meson8b_clkc_init_common()
3886 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3888 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3890 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",