Lines Matching +full:0 +full:x40c
21 * So we model these clocks' rate as 0, to denote it's not an actual rate.
23 #define DUMMY_RATE 0
483 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
488 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
490 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
492 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
494 0x0040, 24, 3, 31),
497 0x0050, 0, 2, 7),
499 0x0050, 8, 4, 15),
501 0x0050, 16, 3, 23),
503 0x0050, 24, 3, 31),
505 0x0060, 0, 1, 7),
508 0x0060, 8, 3, 15),
510 0x0060, 16, 2, 23),
512 0x0060, 24, 3, 31),
515 0x0070, 0, 3, 7),
517 0x0070, 8, 3, 15),
519 0x0070, 16, 1, 23),
521 0x0070, 24, 3, 31),
524 0x0080, 0, 4, 7),
526 0x0080, 8, 2, 15),
528 0x0080, 16, 3, 23),
530 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
533 0x0090, 0, 3, 7),
535 0x0090, 8, 2, 15),
537 0x0090, 16, 3, 23),
540 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
542 0x00A0, 8, 3, 15),
544 0x00A0, 24, 2, 31),
547 0x00B0, 0, 3, 7),
549 0x00B0, 8, 2, 15),
551 0x00B0, 16, 3, 23),
553 0x00B0, 24, 3, 31),
556 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
558 0x00C0, 8, 2, 15),
560 0x00C0, 16, 2, 23),
562 0x00C0, 24, 3, 31),
565 0x00D0, 0, 2, 7),
567 0x00D0, 16, 2, 23),
569 0x00D0, 24, 3, 31),
572 0x00E0, 0, 1, 7),
574 0x00E0, 8, 3, 15),
576 0x00E0, 16, 4, 23),
579 0x00E0, 24, 3, 31),
581 0x00F0, 0, 3, 7),
583 0x00F0, 8, 2, 15),
585 0x00F0, 16, 1, 23),
588 0x0100, 0, 3),
591 0x012c, 0, 3),
593 0x012c, 3, 3),
595 0x012c, 6, 3),
597 0x012c, 15, 1, 23),
599 0x012c, 16, 1, 24),
601 0x012c, 17, 1, 25),
603 0x012c, 18, 1, 26),
605 0x012c, 19, 1, 27),
607 0x012c, 20, 1, 28),
612 0x0120, 0, 8),
614 0x0120, 8, 8),
616 0x0120, 16, 8),
618 0x0120, 24, 8),
620 0x0124, 0, 8),
622 0x0124, 8, 8),
624 0x0124, 16, 8),
626 0x0124, 24, 8),
628 0x0128, 0, 8),
630 0x0128, 8, 8),
634 .sta_ofs = 0x012C,
665 base = devm_platform_ioremap_resource(pdev, 0); in mtk_topckgen_init()
691 .set_ofs = 0x0040,
692 .clr_ofs = 0x0044,
693 .sta_ofs = 0x0048,
700 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
724 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
725 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
751 for (i = 0; i < CLK_INFRA_NR; i++) in mtk_infrasys_init_early()
778 for (i = 0; i < CLK_INFRA_NR; i++) { in mtk_infrasys_init()
794 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); in mtk_infrasys_init()
796 return 0; in mtk_infrasys_init()
800 .set_ofs = 0x0008,
801 .clr_ofs = 0x0010,
802 .sta_ofs = 0x0018,
806 .set_ofs = 0x000c,
807 .clr_ofs = 0x0014,
808 .sta_ofs = 0x001c,
849 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
862 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
872 0x40c, 0, 1),
874 0x40c, 1, 1),
876 0x40c, 2, 1),
878 0x40c, 3, 1),
888 base = devm_platform_ioremap_resource(pdev, 0); in mtk_pericfg_init()
907 return 0; in mtk_pericfg_init()
932 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
933 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
934 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
935 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
936 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
937 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
938 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
939 21, 0x230, 4, 0x0, 0x234, 0),
940 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
941 21, 0x240, 4, 0x0, 0x244, 0),
942 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
943 21, 0x250, 4, 0x0, 0x254, 0),
944 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
945 31, 0x270, 4, 0x0, 0x274, 0),
946 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
947 31, 0x280, 4, 0x0, 0x284, 0),
948 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
949 31, 0x290, 4, 0x0, 0x294, 0),
950 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
951 31, 0x2a0, 4, 0x0, 0x2a4, 0),
952 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
953 31, 0x2b0, 4, 0x0, 0x2b4, 0),
954 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
955 31, 0x2c0, 4, 0x0, 0x2c4, 0),
956 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
957 21, 0x2d0, 4, 0x0, 0x2d4, 0),