Lines Matching +full:i2c +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/ingenic,jz4755-cgu.h>
33 0x0, 0x1, -1, 0x3,
80 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
89 CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
98 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
107 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
116 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
125 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
134 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
143 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
144 .gate = { CGU_REG_CLKGR, 10 },
150 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
151 .gate = { CGU_REG_CLKGR, 9 },
157 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
164 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
170 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
171 .gate = { CGU_REG_CLKGR, 4 },
178 .gate = { CGU_REG_CLKGR, 18 },
185 .gate = { CGU_REG_CLKGR, 2 },
191 .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
192 .gate = { CGU_REG_CLKGR, 8 },
195 /* Gate-only clocks */
200 .gate = { CGU_REG_CLKGR, 0 },
206 .gate = { CGU_REG_CLKGR, 14 },
212 .gate = { CGU_REG_CLKGR, 15 },
218 .gate = { CGU_REG_CLKGR, 7 },
224 .gate = { CGU_REG_CLKGR, 5 },
228 "i2c", CGU_CLK_GATE,
230 .gate = { CGU_REG_CLKGR, 3 },
236 .gate = { CGU_REG_CLKGR, 11 },
242 .gate = { CGU_REG_CLKGR, 1 },
248 .gate = { CGU_REG_CLKGR, 12 },
254 .gate = { CGU_REG_CLKGR, 6 },
260 .gate = { CGU_REG_CLKGR, 16 },
266 .gate = { CGU_REG_CLKGR, 24 },
272 .gate = { CGU_REG_CLKGR, 23 },
278 .gate = { CGU_REG_CLKGR, 22 },
284 .gate = { CGU_REG_CLKGR, 21 },
290 .gate = { CGU_REG_CLKGR, 20 },
296 .gate = { CGU_REG_CLKGR, 19 },
302 .gate = { CGU_REG_CLKGR, 17 },
308 .gate = { CGU_REG_CLKGR, 13 },
321 .gate = { CGU_REG_OPCR, 6, true },
344 * in the case where the device node is compatible with "simple-mfd".
346 CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);