412 	u32 div_reg, div;  in ingenic_clk_recalc_rate()  local
418 		if (!(clk_info->div.bypass_mask & BIT(parent))) {  in ingenic_clk_recalc_rate()
419 			div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
420 			div = (div_reg >> clk_info->div.shift) &  in ingenic_clk_recalc_rate()
421 			      GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_recalc_rate()
423 			if (clk_info->div.div_table)  in ingenic_clk_recalc_rate()
424 				div = clk_info->div.div_table[div];  in ingenic_clk_recalc_rate()
426 				div = (div + 1) * clk_info->div.div;  in ingenic_clk_recalc_rate()
428 			rate /= div;  in ingenic_clk_recalc_rate()
431 		rate /= clk_info->fixdiv.div;  in ingenic_clk_recalc_rate()
439 			unsigned int div)  in ingenic_clk_calc_hw_div()  argument
443 	for (i = 0; i < (1 << clk_info->div.bits)  in ingenic_clk_calc_hw_div()
444 				&& clk_info->div.div_table[i]; i++) {  in ingenic_clk_calc_hw_div()
445 		if (clk_info->div.div_table[i] >= div &&  in ingenic_clk_calc_hw_div()
446 		    clk_info->div.div_table[i] < best) {  in ingenic_clk_calc_hw_div()
447 			best = clk_info->div.div_table[i];  in ingenic_clk_calc_hw_div()
450 			if (div == best)  in ingenic_clk_calc_hw_div()
463 	unsigned int div, hw_div;  in ingenic_clk_calc_div()  local
467 	if (clk_info->div.bypass_mask & BIT(parent))  in ingenic_clk_calc_div()
471 	div = DIV_ROUND_UP(parent_rate, req_rate);  in ingenic_clk_calc_div()
473 	if (clk_info->div.div_table) {  in ingenic_clk_calc_div()
474 		hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_calc_div()
476 		return clk_info->div.div_table[hw_div];  in ingenic_clk_calc_div()
480 	div = clamp_t(unsigned int, div, clk_info->div.div,  in ingenic_clk_calc_div()
481 		      clk_info->div.div << clk_info->div.bits);  in ingenic_clk_calc_div()
488 	div = DIV_ROUND_UP(div, clk_info->div.div);  in ingenic_clk_calc_div()
489 	div *= clk_info->div.div;  in ingenic_clk_calc_div()
491 	return div;  in ingenic_clk_calc_div()
499 	unsigned int div = 1;  in ingenic_clk_determine_rate()  local
502 		div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate,  in ingenic_clk_determine_rate()
505 		div = clk_info->fixdiv.div;  in ingenic_clk_determine_rate()
509 	req->rate = DIV_ROUND_UP(req->best_parent_rate, div);  in ingenic_clk_determine_rate()
518 	return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,  in ingenic_clk_check_stable()
519 				  !(reg & BIT(clk_info->div.busy_bit)),  in ingenic_clk_check_stable()
531 	unsigned int hw_div, div;  in ingenic_clk_set_rate()  local
536 		div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate);  in ingenic_clk_set_rate()
537 		rate = DIV_ROUND_UP(parent_rate, div);  in ingenic_clk_set_rate()
542 		if (clk_info->div.div_table)  in ingenic_clk_set_rate()
543 			hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_set_rate()
545 			hw_div = ((div / clk_info->div.div) - 1);  in ingenic_clk_set_rate()
548 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
551 		mask = GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_set_rate()
552 		reg &= ~(mask << clk_info->div.shift);  in ingenic_clk_set_rate()
553 		reg |= hw_div << clk_info->div.shift;  in ingenic_clk_set_rate()
556 		if (clk_info->div.stop_bit != -1)  in ingenic_clk_set_rate()
557 			reg &= ~BIT(clk_info->div.stop_bit);  in ingenic_clk_set_rate()
560 		if (clk_info->div.ce_bit != -1)  in ingenic_clk_set_rate()
561 			reg |= BIT(clk_info->div.ce_bit);  in ingenic_clk_set_rate()
564 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
567 		if (clk_info->div.busy_bit != -1)  in ingenic_clk_set_rate()