Lines Matching +full:0 +full:x9c
14 { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, },
15 { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, },
16 { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, },
17 { HIX5HD2_FIXED_24M, "24m", NULL, 0, 24000000, },
18 { HIX5HD2_FIXED_600M, "600m", NULL, 0, 600000000, },
19 { HIX5HD2_FIXED_300M, "300m", NULL, 0, 300000000, },
20 { HIX5HD2_FIXED_75M, "75m", NULL, 0, 75000000, },
21 { HIX5HD2_FIXED_200M, "200m", NULL, 0, 200000000, },
22 { HIX5HD2_FIXED_100M, "100m", NULL, 0, 100000000, },
23 { HIX5HD2_FIXED_40M, "40m", NULL, 0, 40000000, },
24 { HIX5HD2_FIXED_150M, "150m", NULL, 0, 150000000, },
25 { HIX5HD2_FIXED_1728M, "1728m", NULL, 0, 1728000000, },
26 { HIX5HD2_FIXED_28P8M, "28p8m", NULL, 0, 28000000, },
27 { HIX5HD2_FIXED_432M, "432m", NULL, 0, 432000000, },
28 { HIX5HD2_FIXED_345P6M, "345p6m", NULL, 0, 345000000, },
29 { HIX5HD2_FIXED_288M, "288m", NULL, 0, 288000000, },
30 { HIX5HD2_FIXED_60M, "60m", NULL, 0, 60000000, },
31 { HIX5HD2_FIXED_750M, "750m", NULL, 0, 750000000, },
32 { HIX5HD2_FIXED_500M, "500m", NULL, 0, 500000000, },
33 { HIX5HD2_FIXED_54M, "54m", NULL, 0, 54000000, },
34 { HIX5HD2_FIXED_27M, "27m", NULL, 0, 27000000, },
35 { HIX5HD2_FIXED_1500M, "1500m", NULL, 0, 1500000000, },
36 { HIX5HD2_FIXED_375M, "375m", NULL, 0, 375000000, },
37 { HIX5HD2_FIXED_187M, "187m", NULL, 0, 187000000, },
38 { HIX5HD2_FIXED_250M, "250m", NULL, 0, 250000000, },
39 { HIX5HD2_FIXED_125M, "125m", NULL, 0, 125000000, },
40 { HIX5HD2_FIXED_2P02M, "2m", NULL, 0, 2000000, },
41 { HIX5HD2_FIXED_50M, "50m", NULL, 0, 50000000, },
42 { HIX5HD2_FIXED_25M, "25m", NULL, 0, 25000000, },
43 { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, },
48 static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
52 static u32 sdio_mux_table[] = {0, 1, 2, 3};
55 static u32 fephy_mux_table[] = {0, 1};
60 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
62 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
64 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
75 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
82 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
85 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
87 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
89 CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
91 { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, },
92 { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
94 CLK_SET_RATE_PARENT, 0x120, 0, 0, },
97 CLK_SET_RATE_PARENT, 0x178, 0, 0, },
99 CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
102 CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
104 CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, },
106 CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
108 CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, },
110 CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
112 CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, },
114 CLK_SET_RATE_PARENT, 0x06c, 16, 0, },
116 CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, },
118 CLK_SET_RATE_PARENT, 0x06c, 20, 0, },
120 CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, },
122 CLK_SET_RATE_PARENT, 0x06c, 0, 0, },
124 CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, },
158 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
160 0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER},
162 0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX},
164 0xb8, 0xff, 0x3f000, 0xbc, 0x7, 0x3f00, TYPE_COMPLEX},
195 return 0; in clk_ether_prepare()
228 return 0; in clk_complex_enable()
259 for (i = 0; i < nums; i++) { in hix5hd2_clk_register_complex()
274 init.flags = 0; in hix5hd2_clk_register_complex()
277 init.num_parents = (clks[i].parent_name ? 1 : 0); in hix5hd2_clk_register_complex()