270 	  ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
273 	  ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
276 	  ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
279 	  ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
282 	  ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
285 	  ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
288 	  ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
291 	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
294 	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
297 	  ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
300 	  ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
303 	  ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
306 	  ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
309 	  ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
312 	  ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2,
315 	  ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2,
318 	  ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
321 	  ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
324 	  ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
327 	  ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1,
330 	  ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
440 	  ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
443 	  ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
477 	int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);  in hi3660_clk_iomcu_init()
484 				   ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),  in hi3660_clk_iomcu_init()
491 	int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);  in hi3660_clk_pmuctrl_init()
498 			       ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);  in hi3660_clk_pmuctrl_init()
504 	int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);  in hi3660_clk_pctrl_init()
510 			       ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);  in hi3660_clk_pctrl_init()
516 	int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +  in hi3660_clk_sctrl_init()
517 		 ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +  in hi3660_clk_sctrl_init()
518 		 ARRAY_SIZE(hi3660_sctrl_mux_clks) +  in hi3660_clk_sctrl_init()
519 		 ARRAY_SIZE(hi3660_sctrl_divider_clks);  in hi3660_clk_sctrl_init()
525 			       ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);  in hi3660_clk_sctrl_init()
527 				   ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),  in hi3660_clk_sctrl_init()
530 			      ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);  in hi3660_clk_sctrl_init()
532 				  ARRAY_SIZE(hi3660_sctrl_divider_clks),  in hi3660_clk_sctrl_init()
538 	int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +  in hi3660_clk_crgctrl_early_init()
539 		 ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +  in hi3660_clk_crgctrl_early_init()
540 		 ARRAY_SIZE(hi3660_crgctrl_gate_clks) +  in hi3660_clk_crgctrl_early_init()
541 		 ARRAY_SIZE(hi3660_crgctrl_mux_clks) +  in hi3660_clk_crgctrl_early_init()
542 		 ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +  in hi3660_clk_crgctrl_early_init()
543 		 ARRAY_SIZE(hi3660_crgctrl_divider_clks);  in hi3660_clk_crgctrl_early_init()
554 				     ARRAY_SIZE(hi3660_fixed_rate_clks),  in hi3660_clk_crgctrl_early_init()
573 				   ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),  in hi3660_clk_crgctrl_init()
576 			       ARRAY_SIZE(hi3660_crgctrl_gate_clks),  in hi3660_clk_crgctrl_init()
579 			      ARRAY_SIZE(hi3660_crgctrl_mux_clks),  in hi3660_clk_crgctrl_init()
582 				       ARRAY_SIZE(hi3660_crg_fixed_factor_clks),  in hi3660_clk_crgctrl_init()
585 				  ARRAY_SIZE(hi3660_crgctrl_divider_clks),  in hi3660_clk_crgctrl_init()