Lines Matching defs:xilly_channel

44 struct xilly_channel {  struct
45 	struct xilly_endpoint *endpoint;
46 	int chan_num;
47 	int log2_element_size;
48 	int seekable;
50 	struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
51 	int num_wr_buffers;
52 	unsigned int wr_buf_size; /* In bytes */
53 	int wr_fpga_buf_idx;
54 	int wr_host_buf_idx;
55 	int wr_host_buf_pos;
56 	int wr_empty;
57 	int wr_ready; /* Significant only when wr_empty == 1 */
58 	int wr_sleepy;
59 	int wr_eof;
60 	int wr_hangup;
61 	spinlock_t wr_spinlock;
62 	struct mutex wr_mutex;
63 	wait_queue_head_t wr_wait;
64 	wait_queue_head_t wr_ready_wait;
65 	int wr_ref_count;
66 	int wr_synchronous;
67 	int wr_allow_partial;
68 	int wr_exclusive_open;
69 	int wr_supports_nonempty;
71 	struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
72 	int num_rd_buffers;
73 	unsigned int rd_buf_size; /* In bytes */
74 	int rd_fpga_buf_idx;
75 	int rd_host_buf_pos;
76 	int rd_host_buf_idx;
77 	int rd_full;
101 	struct xilly_channel **channels;  argument