Lines Matching +full:isa +full:- +full:base

3 * 3780i.h -- declarations for 3780i.c
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
45 * 10/23/2000 - Alpha Release
55 #define DSP_IsaSlaveControl        0x0000	/* ISA slave control register */
56 #define DSP_IsaSlaveStatus         0x0001	/* ISA slave status register */
62 #define DSP_MsaDataDSISHigh        0x0008	/* MSA data register: d-store word or high byte of i-stor…
63 #define DSP_MsaDataISLow           0x000A	/* MSA data register: low word of i-store */
76 	unsigned short EnableDspInt:1;	/* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
80 	unsigned short IsaPacingTimer:12;	/* R: ISA access pacing timer: count of core cycles stolen */
89 #define DSP_BusMasterCfg1Index     0x0009	/* ISA bus master config register 1 */
90 #define DSP_BusMasterCfg2Index     0x000A	/* ISA bus master config register 2 */
91 #define DSP_IsaProtCfgIndex        0x000F	/* ISA protocol control register */
99 	unsigned char BaseIO:2;	/* RW: Base I/O selection */
112 	unsigned char AccessMode:1;	/* RW: 16-bit register access method 0=byte, 1=word */
124 	unsigned char NumTransfers:2;	/* RW: Maximum # of transfers once being granted the ISA bus */
125 …unsigned char ReRequest:2;	/* RW: Minimum delay between releasing the ISA bus and requesting it ag…
126 	unsigned char MEMCS16:1;	/* RW: ISA signal MEMCS16: 0=disabled, 1=enabled */
130 	unsigned char IsaMemCmdWidth:2;	/* RW: ISA memory command width */
184 	unsigned short IsaMaster:1;	/* RW: Reset ISA master interface */
266 	/* Location of base configuration register */
274 	/* IRQ, DMA, and Base I/O addresses for various DSP components */