97 	u32 property, ranges[4];  in tegra_gmi_parse_dt()  local
150 		err = of_property_read_u32(child, "reg", &property);  in tegra_gmi_parse_dt()
157 		property = ranges[1];  in tegra_gmi_parse_dt()
161 	if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {  in tegra_gmi_parse_dt()
162 		dev_err(gmi->dev, "invalid chip select: %d", property);  in tegra_gmi_parse_dt()
167 	gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);  in tegra_gmi_parse_dt()
170 	if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))  in tegra_gmi_parse_dt()
171 		gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);  in tegra_gmi_parse_dt()
175 	if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))  in tegra_gmi_parse_dt()
176 		gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);  in tegra_gmi_parse_dt()
180 	if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))  in tegra_gmi_parse_dt()
181 		gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);  in tegra_gmi_parse_dt()
185 	if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))  in tegra_gmi_parse_dt()
186 		gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);  in tegra_gmi_parse_dt()
190 	if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))  in tegra_gmi_parse_dt()
191 		gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);  in tegra_gmi_parse_dt()
195 	if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))  in tegra_gmi_parse_dt()
196 		gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);  in tegra_gmi_parse_dt()
200 	if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))  in tegra_gmi_parse_dt()
201 		gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);  in tegra_gmi_parse_dt()