Lines Matching +full:cell +full:- +full:count
1 /* SPDX-License-Identifier: GPL-2.0 */
56 #define NUM_HB 8 /* Pre-allocated huge buffers */
59 /* Lower level for count of buffers */
65 /* Upper level for count of buffers */
107 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
108 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
111 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
112 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
114 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
122 * RSQ - Receive Status Queue
135 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
137 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
151 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
153 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
155 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
157 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
159 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
161 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
163 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
166 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
168 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
174 * RCQ - Raw Cell Queue
194 (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
196 (le32_to_cpu((ns_rcqep)->word_1))
198 (le32_to_cpu((ns_rcqep)->word_2))
201 * SCQ - Segmentation Channel Queue
250 (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
260 * TSQ - Transmit Status Queue
278 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
280 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
283 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
292 (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
294 ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
296 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
301 * RCT - Receive Connection Table
339 * FBD - Free Buffer Descriptor
350 * TST - Transmit Schedule Table
359 #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
360 #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
368 - When the opcode is FIXED, sramad specifies the SRAM address of the
370 - When the opcode is END, sramad specifies the SRAM address of the
375 * SCD - Segmentation Channel Descriptor
438 CDC = 0x28, /* Cell Drop Counter R/clear */
439 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
440 ICC = 0x30, /* Invalid Cell Count R/clear */
441 RAWCT = 0x34, /* Raw Cell Tail R */
459 /* b19{1=open,0=close} b18-2{SRAM addr} */
462 /* b18-2{SRAM addr} b1-0{burst size} */
465 /* b18-2{SRAM addr} */
471 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
474 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
488 #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
492 #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
495 #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
504 #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
506 #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
542 #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
543 #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
554 #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
569 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
648 (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->buf_type)
650 (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->dma)
652 (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->iovcnt)
689 volatile int count; /* number of buffers in the queue */ member
693 /* NOTE: for small and large buffer pools, the count is not used, as the
724 skb_pool hbpool; /* Pre-allocated huge buffers */
742 struct sk_buff *rcbuf; /* Current raw cell buffer */
744 u32 rawch; /* Raw cell queue head */