Lines Matching refs:readl
468 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_dma_prep()
502 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_nodata_prep()
535 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
538 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ in __pdc20621_push_hdma()
588 readl(dimm_mmio), readl(dimm_mmio + 4), in pdc20621_dump_hdma()
589 readl(dimm_mmio + 8), readl(dimm_mmio + 12)); in pdc20621_dump_hdma()
621 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in pdc20621_packet_start()
625 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); in pdc20621_packet_start()
672 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
683 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
698 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
702 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); in pdc20621_host_intr()
705 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); in pdc20621_host_intr()
711 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
756 mask = readl(mmio_base + PDC_20621_SEQMASK); in pdc20621_interrupt()
800 tmp = readl(mmio + PDC_CTLSTAT); in pdc_freeze()
804 readl(mmio + PDC_CTLSTAT); /* flush */ in pdc_freeze()
818 tmp = readl(mmio + PDC_CTLSTAT); in pdc_thaw()
821 readl(mmio + PDC_CTLSTAT); /* flush */ in pdc_thaw()
833 tmp = readl(mmio); in pdc_reset_port()
845 readl(mmio); /* flush */ in pdc_reset_port()
954 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_get_from_dimm()
956 readl(mmio + PDC_DIMM_WINDOW_CTLR); in pdc20621_get_from_dimm()
968 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_get_from_dimm()
970 readl(mmio + PDC_DIMM_WINDOW_CTLR); in pdc20621_get_from_dimm()
979 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_get_from_dimm()
981 readl(mmio + PDC_DIMM_WINDOW_CTLR); in pdc20621_get_from_dimm()
1005 readl(mmio + PDC_DIMM_WINDOW_CTLR); in pdc20621_put_to_dimm()
1012 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_put_to_dimm()
1018 readl(mmio + PDC_DIMM_WINDOW_CTLR); in pdc20621_put_to_dimm()
1021 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_put_to_dimm()
1029 readl(mmio + PDC_DIMM_WINDOW_CTLR); in pdc20621_put_to_dimm()
1032 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_put_to_dimm()
1053 readl(mmio + PDC_I2C_ADDR_DATA); in pdc20621_i2c_read()
1060 status = readl(mmio + PDC_I2C_CONTROL); in pdc20621_i2c_read()
1062 status = readl(mmio + PDC_I2C_ADDR_DATA); in pdc20621_i2c_read()
1153 readl(mmio + PDC_DIMM0_CONTROL); in pdc20621_prog_dimm0()
1176 readl(mmio + PDC_SDRAM_CONTROL); in pdc20621_prog_dimm_global()
1189 readl(mmio + PDC_SDRAM_CONTROL); in pdc20621_prog_dimm_global()
1200 data = readl(mmio + PDC_SDRAM_CONTROL); in pdc20621_prog_dimm_global()
1229 time_period = readl(mmio + PDC_TIME_PERIOD); in pdc20621_dimm_init()
1234 readl(mmio + PDC_TIME_CONTROL); in pdc20621_dimm_init()
1244 tcount = readl(mmio + PDC_TIME_COUNTER); in pdc20621_dimm_init()
1275 readl(mmio + PDC_CTL_STATUS); in pdc20621_dimm_init()
1367 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000; in pdc_20621_init()
1374 tmp = readl(mmio + PDC_HDMA_CTLSTAT); in pdc_20621_init()
1377 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ in pdc_20621_init()
1381 tmp = readl(mmio + PDC_HDMA_CTLSTAT); in pdc_20621_init()
1384 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ in pdc_20621_init()