Lines Matching refs:sil_port
230 } sil_port[] = { variable
255 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_stop()
281 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_start()
349 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; in sil_set_mode()
517 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); in sil_interrupt()
542 writel(0, mmio_base + sil_port[ap->port_no].sien); in sil_freeze()
575 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); in sil_thaw()
665 mmio_base + sil_port[i].fifo_cfg); in sil_init_controller()
675 tmp = readl(mmio_base + sil_port[i].sfis_cfg); in sil_init_controller()
681 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); in sil_init_controller()
688 tmp = readl(mmio_base + sil_port[2].bmdma); in sil_init_controller()
691 mmio_base + sil_port[2].bmdma); in sil_init_controller()
771 ioaddr->cmd_addr = mmio_base + sil_port[i].tf; in sil_init_one()
773 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; in sil_init_one()
774 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; in sil_init_one()
775 ioaddr->scr_addr = mmio_base + sil_port[i].scr; in sil_init_one()
779 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf"); in sil_init_one()