41  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
50  * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
62 	{ XFER_UDMA_6,		0x12446231 },	/* 0x12646231 ?? */
63 	{ XFER_UDMA_5,		0x12446231 },
64 	{ XFER_UDMA_4,		0x12446231 },
65 	{ XFER_UDMA_3,		0x126c6231 },
66 	{ XFER_UDMA_2,		0x12486231 },
67 	{ XFER_UDMA_1,		0x124c6233 },
68 	{ XFER_UDMA_0,		0x12506297 },
70 	{ XFER_MW_DMA_2,	0x22406c31 },
71 	{ XFER_MW_DMA_1,	0x22406c33 },
72 	{ XFER_MW_DMA_0,	0x22406c97 },
74 	{ XFER_PIO_4,		0x06414e31 },
75 	{ XFER_PIO_3,		0x06414e42 },
76 	{ XFER_PIO_2,		0x06414e53 },
77 	{ XFER_PIO_1,		0x06814e93 },
78 	{ XFER_PIO_0,		0x06814ea7 }
82 	{ XFER_UDMA_6,		0x12848242 },
83 	{ XFER_UDMA_5,		0x12848242 },
84 	{ XFER_UDMA_4,		0x12ac8242 },
85 	{ XFER_UDMA_3,		0x128c8242 },
86 	{ XFER_UDMA_2,		0x120c8242 },
87 	{ XFER_UDMA_1,		0x12148254 },
88 	{ XFER_UDMA_0,		0x121882ea },
90 	{ XFER_MW_DMA_2,	0x22808242 },
91 	{ XFER_MW_DMA_1,	0x22808254 },
92 	{ XFER_MW_DMA_0,	0x228082ea },
94 	{ XFER_PIO_4,		0x0a81f442 },
95 	{ XFER_PIO_3,		0x0a81f443 },
96 	{ XFER_PIO_2,		0x0a81f454 },
97 	{ XFER_PIO_1,		0x0ac1f465 },
98 	{ XFER_PIO_0,		0x0ac1f48a }
102 	{ XFER_UDMA_6,		0x1c869c62 },
103 	{ XFER_UDMA_5,		0x1cae9c62 },	/* 0x1c8a9c62 */
104 	{ XFER_UDMA_4,		0x1c8a9c62 },
105 	{ XFER_UDMA_3,		0x1c8e9c62 },
106 	{ XFER_UDMA_2,		0x1c929c62 },
107 	{ XFER_UDMA_1,		0x1c9a9c62 },
108 	{ XFER_UDMA_0,		0x1c829c62 },
110 	{ XFER_MW_DMA_2,	0x2c829c62 },
111 	{ XFER_MW_DMA_1,	0x2c829c66 },
112 	{ XFER_MW_DMA_0,	0x2c829d2e },
114 	{ XFER_PIO_4,		0x0c829c62 },
115 	{ XFER_PIO_3,		0x0c829c84 },
116 	{ XFER_PIO_2,		0x0c829ca6 },
117 	{ XFER_PIO_1,		0x0d029d26 },
118 	{ XFER_PIO_0,		0x0d029d5e }
218 	return 0xffffffffU;	/* silence compiler warning */  in hpt37x_find_mode()
230 	if (i >= 0) {  in hpt_dma_blacklisted()
235 	return 0;  in hpt_dma_blacklisted()
264 	"IC35L010AVER07-0",
265 	"IC35L020AVER07-0",
266 	"IC35L030AVER07-0",
267 	"IC35L040AVER07-0",
268 	"IC35L060AVER07-0",
287 			mask &= ~(0xE0 << ATA_SHIFT_UDMA);  in hpt370_filter()
304 			mask &= ~(0xE0 << ATA_SHIFT_UDMA);  in hpt370a_filter()
320 		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);  in hpt372_filter()
337 	pci_read_config_byte(pdev, 0x5B, &scr2);  in hpt37x_cable_detect()
338 	pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);  in hpt37x_cable_detect()
343 	pci_read_config_byte(pdev, 0x5A, &ata66);  in hpt37x_cable_detect()
345 	pci_write_config_byte(pdev, 0x5B, scr2);  in hpt37x_cable_detect()
363 	unsigned int mcrbase = 0x50 + 4 * ap->port_no;  in hpt374_fn1_cable_detect()
369 	/* Set bit 15 of 0x52 to enable TCBLID as input */  in hpt374_fn1_cable_detect()
370 	pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);  in hpt374_fn1_cable_detect()
371 	pci_read_config_byte(pdev, 0x5A, &ata66);  in hpt374_fn1_cable_detect()
394 		{ 0x50, 1, 0x04, 0x04 },  in hpt37x_pre_reset()
395 		{ 0x54, 1, 0x04, 0x04 }  in hpt37x_pre_reset()
403 	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);  in hpt37x_pre_reset()
408 	 * on interrupts. (== 0x01 despite what the docs say)  in hpt37x_pre_reset()
410 	pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);  in hpt37x_pre_reset()
413 		mcr2 &= ~0x02;  in hpt37x_pre_reset()
414 		mcr2 |= 0x01;  in hpt37x_pre_reset()
416 		mcr2 &= ~0x07;  in hpt37x_pre_reset()
418 	pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);  in hpt37x_pre_reset()
427 	int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);  in hpt37x_set_mode()
432 		mask = 0xcfc3ffff;  in hpt37x_set_mode()
434 		mask = 0x31c001ff;  in hpt37x_set_mode()
436 		mask = 0x303c0000;  in hpt37x_set_mode()
491 		pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);  in hpt370_bmdma_stop()
501 		pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);  in hpt370_bmdma_stop()
518 	int mscreg = 0x50 + 4 * ap->port_no;  in hpt37x_bmdma_stop()
521 	pci_read_config_byte(pdev, 0x6A, &bwsr_stat);  in hpt37x_bmdma_stop()
524 		pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);  in hpt37x_bmdma_stop()
597  *	Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
604 		return 0;	/* 33Mhz slot */  in hpt37x_clock_slot()
626 	for (tries = 0; tries < 0x5000; tries++) {  in hpt37x_calibrate_dpll()
628 		pci_read_config_byte(dev, 0x5b, &reg5b);  in hpt37x_calibrate_dpll()
629 		if (reg5b & 0x80) {  in hpt37x_calibrate_dpll()
631 			for (tries = 0; tries < 0x1000; tries++) {  in hpt37x_calibrate_dpll()
632 				pci_read_config_byte(dev, 0x5b, &reg5b);  in hpt37x_calibrate_dpll()
634 				if ((reg5b & 0x80) == 0)  in hpt37x_calibrate_dpll()
635 					return 0;  in hpt37x_calibrate_dpll()
638 			pci_read_config_dword(dev, 0x5c, &reg5c);  in hpt37x_calibrate_dpll()
639 			pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);  in hpt37x_calibrate_dpll()
644 	return 0;  in hpt37x_calibrate_dpll()
655 	 * from FN 0 on the HPT374.  in hpt37x_pci_clock()
664 			return 0;  in hpt37x_pci_clock()
665 		fcnt = inl(pci_resource_start(pdev_fn0, 4) + 0x90);  in hpt37x_pci_clock()
668 		fcnt = inl(pci_resource_start(pdev, 4) + 0x90);  in hpt37x_pci_clock()
671 	if ((fcnt >> 12) != 0xABCDE) {  in hpt37x_pci_clock()
672 		u32 total = 0;  in hpt37x_pci_clock()
679 		for (i = 0; i < 128; i++) {  in hpt37x_pci_clock()
680 			pci_read_config_word(pdev, 0x78, &sr);  in hpt37x_pci_clock()
681 			total += sr & 0x1FF;  in hpt37x_pci_clock()
686 	fcnt &= 0x1FF;  in hpt37x_pci_clock()
714  *	HPT366			4 (HPT366)	0	Other driver
829 			ppi[0] = &info_hpt370;  in hpt37x_init_one()
831 			prefer_dpll = 0;  in hpt37x_init_one()
834 			ppi[0] = &info_hpt370a;  in hpt37x_init_one()
836 			prefer_dpll = 0;  in hpt37x_init_one()
839 			ppi[0] = &info_hpt372;  in hpt37x_init_one()
853 		ppi[0] = &info_hpt372;  in hpt37x_init_one()
860 		ppi[0] = &info_hpt302;  in hpt37x_init_one()
867 		ppi[0] = &info_hpt302;  in hpt37x_init_one()
873 		pci_read_config_byte(dev, 0x50, &mcr1);  in hpt37x_init_one()
874 		mcr1 &= ~0x04;  in hpt37x_init_one()
875 		pci_write_config_byte(dev, 0x50, mcr1);  in hpt37x_init_one()
892 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);  in hpt37x_init_one()
893 	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);  in hpt37x_init_one()
894 	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);  in hpt37x_init_one()
896 	pci_read_config_byte(dev, 0x5A, &irqmask);  in hpt37x_init_one()
897 	irqmask &= ~0x10;  in hpt37x_init_one()
898 	pci_write_config_byte(dev, 0x5a, irqmask);  in hpt37x_init_one()
909 		pci_read_config_byte(dev, 0x50, &mcr1);  in hpt37x_init_one()
910 		mcr1 &= ~0x04;  in hpt37x_init_one()
911 		pci_write_config_byte(dev, 0x50, mcr1);  in hpt37x_init_one()
921 	pci_write_config_byte(dev, 0x5b, 0x23);  in hpt37x_init_one()
928 		outb(0x0e, iobase + 0x9c);  in hpt37x_init_one()
951 		dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;  in hpt37x_init_one()
959 		pci_write_config_byte(dev, 0x5b, 0x21);  in hpt37x_init_one()
960 		pci_write_config_dword(dev, 0x5C,  in hpt37x_init_one()
961 				       (f_high << 16) | f_low | 0x100);  in hpt37x_init_one()
963 		for (adjust = 0; adjust < 8; adjust++) {  in hpt37x_init_one()
974 			pci_write_config_dword(dev, 0x5C,  in hpt37x_init_one()
975 					       (f_high << 16) | f_low | 0x100);  in hpt37x_init_one()
996 		if (clock_slot < 2 && ppi[0] == &info_hpt370)  in hpt37x_init_one()
997 			ppi[0] = &info_hpt370_33;  in hpt37x_init_one()
998 		if (clock_slot < 2 && ppi[0] == &info_hpt370a)  in hpt37x_init_one()
999 			ppi[0] = &info_hpt370a_33;  in hpt37x_init_one()
1006 	return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);  in hpt37x_init_one()