170 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);  in ivpu_pll_cmd_send()
175 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);  in ivpu_pll_cmd_send()
180 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);  in ivpu_pll_cmd_send()
184 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);  in ivpu_pll_cmd_send()
421 		REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);  in ivpu_boot_host_ss_axi_drive()
422 		REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);  in ivpu_boot_host_ss_axi_drive()
666 	REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);  in ivpu_boot_d0i3_drive()
747 	REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);  in ivpu_hw_40xx_reset()
795 	REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);  in ivpu_hw_40xx_profiling_freq_reg_set()
809 	REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);  in ivpu_hw_40xx_clock_relinquish_disable()
989 	REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);  in ivpu_hw_40xx_irq_enable()
990 	REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_40xx_irq_enable()
995 	REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_40xx_irq_disable()
996 	REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);  in ivpu_hw_40xx_irq_disable()
1069 		REGB_WR32(VPU_40XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);  in ivpu_hw_40xx_irqb_handler()
1075 		REGB_WR32(VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR, 0x1);  in ivpu_hw_40xx_irqb_handler()
1081 		REGB_WR32(VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR, 0x1);  in ivpu_hw_40xx_irqb_handler()
1089 		REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR, 0x1);  in ivpu_hw_40xx_irqb_handler()
1097 		REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR, 0x1);  in ivpu_hw_40xx_irqb_handler()
1107 	REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);  in ivpu_hw_40xx_irqb_handler()
1120 	REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_40xx_irq_handler()
1126 	REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_40xx_irq_handler()