145 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val);  in ivpu_pll_cmd_send()
150 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val);  in ivpu_pll_cmd_send()
154 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val);  in ivpu_pll_cmd_send()
158 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val);  in ivpu_pll_cmd_send()
604 	REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val);  in ivpu_boot_d0i3_drive()
647 	REGB_WR32(VPU_37XX_BUTTRESS_VPU_IP_RESET, val);  in ivpu_hw_37xx_reset()
869 	REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);  in ivpu_hw_37xx_irq_enable()
870 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_37xx_irq_enable()
875 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_37xx_irq_disable()
876 	REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);  in ivpu_hw_37xx_irq_disable()
949 		REGB_WR32(VPU_37XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);  in ivpu_hw_37xx_irqb_handler()
960 		REGB_WR32(VPU_37XX_BUTTRESS_UFI_ERR_CLEAR, 0x1);  in ivpu_hw_37xx_irqb_handler()
970 		REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);  in ivpu_hw_37xx_irqb_handler()
972 		REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status);  in ivpu_hw_37xx_irqb_handler()
985 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_37xx_irq_handler()
991 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_37xx_irq_handler()