Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
44 * - checks DMA pointer
45 * - WREG, MSG_PROT are not allowed.
46 * - MSG_LONG/SHORT are allowed.
57 * - PQ entry is in kernel address space and the driver doesn't map it.
58 * - CP writes to MSIX register and to kernel address space (completion
73 #define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb"
74 #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb"
362 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_set_fixed_properties()
365 prop->max_queues = GOYA_QUEUE_ID_SIZE; in goya_set_fixed_properties()
366 prop->hw_queues_props = kcalloc(prop->max_queues, in goya_set_fixed_properties()
370 if (!prop->hw_queues_props) in goya_set_fixed_properties()
371 return -ENOMEM; in goya_set_fixed_properties()
374 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT; in goya_set_fixed_properties()
375 prop->hw_queues_props[i].driver_only = 0; in goya_set_fixed_properties()
376 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL; in goya_set_fixed_properties()
380 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; in goya_set_fixed_properties()
381 prop->hw_queues_props[i].driver_only = 1; in goya_set_fixed_properties()
382 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL; in goya_set_fixed_properties()
387 prop->hw_queues_props[i].type = QUEUE_TYPE_INT; in goya_set_fixed_properties()
388 prop->hw_queues_props[i].driver_only = 0; in goya_set_fixed_properties()
389 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER; in goya_set_fixed_properties()
392 prop->cfg_base_address = CFG_BASE; in goya_set_fixed_properties()
393 prop->device_dma_offset_for_host_access = HOST_PHYS_BASE; in goya_set_fixed_properties()
394 prop->host_base_address = HOST_PHYS_BASE; in goya_set_fixed_properties()
395 prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE; in goya_set_fixed_properties()
396 prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; in goya_set_fixed_properties()
397 prop->completion_mode = HL_COMPLETION_MODE_JOB; in goya_set_fixed_properties()
398 prop->dram_base_address = DRAM_PHYS_BASE; in goya_set_fixed_properties()
399 prop->dram_size = DRAM_PHYS_DEFAULT_SIZE; in goya_set_fixed_properties()
400 prop->dram_end_address = prop->dram_base_address + prop->dram_size; in goya_set_fixed_properties()
401 prop->dram_user_base_address = DRAM_BASE_ADDR_USER; in goya_set_fixed_properties()
403 prop->sram_base_address = SRAM_BASE_ADDR; in goya_set_fixed_properties()
404 prop->sram_size = SRAM_SIZE; in goya_set_fixed_properties()
405 prop->sram_end_address = prop->sram_base_address + prop->sram_size; in goya_set_fixed_properties()
406 prop->sram_user_base_address = prop->sram_base_address + in goya_set_fixed_properties()
409 prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; in goya_set_fixed_properties()
410 prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR; in goya_set_fixed_properties()
411 if (hdev->pldm) in goya_set_fixed_properties()
412 prop->mmu_pgt_size = 0x800000; /* 8MB */ in goya_set_fixed_properties()
414 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE; in goya_set_fixed_properties()
415 prop->mmu_pte_size = HL_PTE_SIZE; in goya_set_fixed_properties()
416 prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE; in goya_set_fixed_properties()
417 prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE; in goya_set_fixed_properties()
418 prop->dram_page_size = PAGE_SIZE_2MB; in goya_set_fixed_properties()
419 prop->device_mem_alloc_default_page_size = prop->dram_page_size; in goya_set_fixed_properties()
420 prop->dram_supports_virtual_memory = true; in goya_set_fixed_properties()
422 prop->dmmu.hop_shifts[MMU_HOP0] = MMU_V1_0_HOP0_SHIFT; in goya_set_fixed_properties()
423 prop->dmmu.hop_shifts[MMU_HOP1] = MMU_V1_0_HOP1_SHIFT; in goya_set_fixed_properties()
424 prop->dmmu.hop_shifts[MMU_HOP2] = MMU_V1_0_HOP2_SHIFT; in goya_set_fixed_properties()
425 prop->dmmu.hop_shifts[MMU_HOP3] = MMU_V1_0_HOP3_SHIFT; in goya_set_fixed_properties()
426 prop->dmmu.hop_shifts[MMU_HOP4] = MMU_V1_0_HOP4_SHIFT; in goya_set_fixed_properties()
427 prop->dmmu.hop_masks[MMU_HOP0] = MMU_V1_0_HOP0_MASK; in goya_set_fixed_properties()
428 prop->dmmu.hop_masks[MMU_HOP1] = MMU_V1_0_HOP1_MASK; in goya_set_fixed_properties()
429 prop->dmmu.hop_masks[MMU_HOP2] = MMU_V1_0_HOP2_MASK; in goya_set_fixed_properties()
430 prop->dmmu.hop_masks[MMU_HOP3] = MMU_V1_0_HOP3_MASK; in goya_set_fixed_properties()
431 prop->dmmu.hop_masks[MMU_HOP4] = MMU_V1_0_HOP4_MASK; in goya_set_fixed_properties()
432 prop->dmmu.start_addr = VA_DDR_SPACE_START; in goya_set_fixed_properties()
433 prop->dmmu.end_addr = VA_DDR_SPACE_END; in goya_set_fixed_properties()
434 prop->dmmu.page_size = PAGE_SIZE_2MB; in goya_set_fixed_properties()
435 prop->dmmu.num_hops = MMU_ARCH_5_HOPS; in goya_set_fixed_properties()
436 prop->dmmu.last_mask = LAST_MASK; in goya_set_fixed_properties()
437 /* TODO: will be duplicated until implementing per-MMU props */ in goya_set_fixed_properties()
438 prop->dmmu.hop_table_size = prop->mmu_hop_table_size; in goya_set_fixed_properties()
439 prop->dmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; in goya_set_fixed_properties()
442 memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu)); in goya_set_fixed_properties()
443 prop->pmmu.start_addr = VA_HOST_SPACE_START; in goya_set_fixed_properties()
444 prop->pmmu.end_addr = VA_HOST_SPACE_END; in goya_set_fixed_properties()
445 prop->pmmu.page_size = PAGE_SIZE_4KB; in goya_set_fixed_properties()
446 prop->pmmu.num_hops = MMU_ARCH_5_HOPS; in goya_set_fixed_properties()
447 prop->pmmu.last_mask = LAST_MASK; in goya_set_fixed_properties()
448 /* TODO: will be duplicated until implementing per-MMU props */ in goya_set_fixed_properties()
449 prop->pmmu.hop_table_size = prop->mmu_hop_table_size; in goya_set_fixed_properties()
450 prop->pmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; in goya_set_fixed_properties()
453 memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); in goya_set_fixed_properties()
454 prop->pmmu_huge.page_size = PAGE_SIZE_2MB; in goya_set_fixed_properties()
456 prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END; in goya_set_fixed_properties()
457 prop->cfg_size = CFG_SIZE; in goya_set_fixed_properties()
458 prop->max_asid = MAX_ASID; in goya_set_fixed_properties()
459 prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE; in goya_set_fixed_properties()
460 prop->high_pll = PLL_HIGH_DEFAULT; in goya_set_fixed_properties()
461 prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT; in goya_set_fixed_properties()
462 prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE; in goya_set_fixed_properties()
463 prop->max_power_default = MAX_POWER_DEFAULT; in goya_set_fixed_properties()
464 prop->dc_power_default = DC_POWER_DEFAULT; in goya_set_fixed_properties()
465 prop->tpc_enabled_mask = TPC_ENABLED_MASK; in goya_set_fixed_properties()
466 prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; in goya_set_fixed_properties()
467 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; in goya_set_fixed_properties()
469 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, in goya_set_fixed_properties()
472 prop->max_pending_cs = GOYA_MAX_PENDING_CS; in goya_set_fixed_properties()
474 prop->first_available_user_interrupt = USHRT_MAX; in goya_set_fixed_properties()
475 prop->tpc_interrupt_id = USHRT_MAX; in goya_set_fixed_properties()
476 prop->eq_interrupt_id = GOYA_EVENT_QUEUE_MSIX_IDX; in goya_set_fixed_properties()
479 prop->first_available_cq[i] = USHRT_MAX; in goya_set_fixed_properties()
481 prop->fw_cpu_boot_dev_sts0_valid = false; in goya_set_fixed_properties()
482 prop->fw_cpu_boot_dev_sts1_valid = false; in goya_set_fixed_properties()
483 prop->hard_reset_done_by_fw = false; in goya_set_fixed_properties()
484 prop->gic_interrupts_enable = true; in goya_set_fixed_properties()
486 prop->server_type = HL_SERVER_TYPE_UNKNOWN; in goya_set_fixed_properties()
488 prop->clk_pll_index = HL_GOYA_MME_PLL; in goya_set_fixed_properties()
490 prop->use_get_power_for_reset_history = true; in goya_set_fixed_properties()
492 prop->configurable_stop_on_err = true; in goya_set_fixed_properties()
494 prop->set_max_power_on_device_init = true; in goya_set_fixed_properties()
496 prop->dma_mask = 48; in goya_set_fixed_properties()
502 * goya_pci_bars_map - Map PCI BARS of Goya device
506 * Request PCI regions and map them to kernel virtual addresses.
520 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + in goya_pci_bars_map()
521 (CFG_BASE - SRAM_BASE_ADDR); in goya_pci_bars_map()
528 struct goya_device *goya = hdev->asic_specific; in goya_set_ddr_bar_base()
533 if ((goya) && (goya->ddr_bar_cur_addr == addr)) in goya_set_ddr_bar_base()
536 /* Inbound Region 1 - Bar 4 - Point to DDR */ in goya_set_ddr_bar_base()
545 old_addr = goya->ddr_bar_cur_addr; in goya_set_ddr_bar_base()
546 goya->ddr_bar_cur_addr = addr; in goya_set_ddr_bar_base()
553 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
566 if (hdev->asic_prop.iatu_done_by_fw) in goya_init_iatu()
569 /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */ in goya_init_iatu()
577 /* Inbound Region 1 - Bar 4 - Point to DDR */ in goya_init_iatu()
585 /* Outbound Region 0 - Point to Host */ in goya_init_iatu()
600 * goya_early_init - GOYA early initialization code
612 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_early_init()
613 struct pci_dev *pdev = hdev->pdev; in goya_early_init()
620 dev_err(hdev->dev, "Failed to get fixed properties\n"); in goya_early_init()
628 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", in goya_early_init()
630 rc = -ENODEV; in goya_early_init()
637 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", in goya_early_init()
639 rc = -ENODEV; in goya_early_init()
643 prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); in goya_early_init()
644 hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID); in goya_early_init()
647 if (hdev->asic_prop.fw_security_enabled) { in goya_early_init()
648 hdev->asic_prop.iatu_done_by_fw = true; in goya_early_init()
660 hdev->asic_prop.iatu_done_by_fw = true; in goya_early_init()
668 * version to determine whether we run with a security-enabled firmware in goya_early_init()
672 if (hdev->reset_on_preboot_fail) in goya_early_init()
674 hdev->asic_funcs->hw_fini(hdev, true, false); in goya_early_init()
679 dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); in goya_early_init()
680 rc = hdev->asic_funcs->hw_fini(hdev, true, false); in goya_early_init()
682 dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc); in goya_early_init()
687 if (!hdev->pldm) { in goya_early_init()
690 dev_warn(hdev->dev, in goya_early_init()
699 kfree(hdev->asic_prop.hw_queues_props); in goya_early_init()
704 * goya_early_fini - GOYA early finalization code
713 kfree(hdev->asic_prop.hw_queues_props); in goya_early_fini()
728 struct goya_device *goya = hdev->asic_specific; in goya_qman0_set_security()
730 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_qman0_set_security()
742 * goya_fetch_psoc_frequency - Fetch PSOC frequency values
749 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_fetch_psoc_frequency()
754 if (hdev->asic_prop.fw_security_enabled) { in goya_fetch_psoc_frequency()
755 struct goya_device *goya = hdev->asic_specific; in goya_fetch_psoc_frequency()
757 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_fetch_psoc_frequency()
789 dev_warn(hdev->dev, in goya_fetch_psoc_frequency()
796 prop->psoc_timestamp_frequency = freq; in goya_fetch_psoc_frequency()
797 prop->psoc_pci_pll_nr = nr; in goya_fetch_psoc_frequency()
798 prop->psoc_pci_pll_nf = nf; in goya_fetch_psoc_frequency()
799 prop->psoc_pci_pll_od = od; in goya_fetch_psoc_frequency()
800 prop->psoc_pci_pll_div_factor = div_fctr; in goya_fetch_psoc_frequency()
804 * goya_set_frequency - set the frequency of the device
818 struct goya_device *goya = hdev->asic_specific; in goya_set_frequency()
820 if ((goya->pm_mng_profile == PM_MANUAL) || in goya_set_frequency()
821 (goya->curr_pll_profile == freq)) in goya_set_frequency()
824 dev_dbg(hdev->dev, "Changing device frequency to %s\n", in goya_set_frequency()
829 goya->curr_pll_profile = freq; in goya_set_frequency()
839 struct hl_device *hdev = goya_work->hdev; in goya_set_freq_to_low_job()
841 mutex_lock(&hdev->fpriv_list_lock); in goya_set_freq_to_low_job()
843 if (!hdev->is_compute_ctx_active) in goya_set_freq_to_low_job()
846 mutex_unlock(&hdev->fpriv_list_lock); in goya_set_freq_to_low_job()
848 schedule_delayed_work(&goya_work->work_freq, in goya_set_freq_to_low_job()
854 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_late_init()
855 struct goya_device *goya = hdev->asic_specific; in goya_late_init()
862 dev_err(hdev->dev, in goya_late_init()
869 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc); in goya_late_init()
887 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc); in goya_late_init()
895 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); in goya_late_init()
899 dev_err(hdev->dev, in goya_late_init()
905 goya->curr_pll_profile = PLL_LOW; in goya_late_init()
907 goya->pm_mng_profile = PM_AUTO; in goya_late_init()
911 schedule_delayed_work(&goya->goya_work->work_freq, in goya_late_init()
918 * goya_late_fini - GOYA late tear-down code
926 struct goya_device *goya = hdev->asic_specific; in goya_late_fini()
928 cancel_delayed_work_sync(&goya->goya_work->work_freq); in goya_late_fini()
935 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_set_pci_memory_regions()
939 region = &hdev->pci_mem_region[PCI_REGION_CFG]; in goya_set_pci_memory_regions()
940 region->region_base = CFG_BASE; in goya_set_pci_memory_regions()
941 region->region_size = CFG_SIZE; in goya_set_pci_memory_regions()
942 region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR; in goya_set_pci_memory_regions()
943 region->bar_size = CFG_BAR_SIZE; in goya_set_pci_memory_regions()
944 region->bar_id = SRAM_CFG_BAR_ID; in goya_set_pci_memory_regions()
945 region->used = 1; in goya_set_pci_memory_regions()
948 region = &hdev->pci_mem_region[PCI_REGION_SRAM]; in goya_set_pci_memory_regions()
949 region->region_base = SRAM_BASE_ADDR; in goya_set_pci_memory_regions()
950 region->region_size = SRAM_SIZE; in goya_set_pci_memory_regions()
951 region->offset_in_bar = 0; in goya_set_pci_memory_regions()
952 region->bar_size = CFG_BAR_SIZE; in goya_set_pci_memory_regions()
953 region->bar_id = SRAM_CFG_BAR_ID; in goya_set_pci_memory_regions()
954 region->used = 1; in goya_set_pci_memory_regions()
957 region = &hdev->pci_mem_region[PCI_REGION_DRAM]; in goya_set_pci_memory_regions()
958 region->region_base = DRAM_PHYS_BASE; in goya_set_pci_memory_regions()
959 region->region_size = hdev->asic_prop.dram_size; in goya_set_pci_memory_regions()
960 region->offset_in_bar = 0; in goya_set_pci_memory_regions()
961 region->bar_size = prop->dram_pci_bar_size; in goya_set_pci_memory_regions()
962 region->bar_id = DDR_BAR_ID; in goya_set_pci_memory_regions()
963 region->used = 1; in goya_set_pci_memory_regions()
967 * goya_sw_init - Goya software initialization code
980 return -ENOMEM; in goya_sw_init()
983 goya->ddr_bar_cur_addr = DRAM_PHYS_BASE; in goya_sw_init()
985 goya->mme_clk = GOYA_PLL_FREQ_LOW; in goya_sw_init()
986 goya->tpc_clk = GOYA_PLL_FREQ_LOW; in goya_sw_init()
987 goya->ic_clk = GOYA_PLL_FREQ_LOW; in goya_sw_init()
989 hdev->asic_specific = goya; in goya_sw_init()
992 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), in goya_sw_init()
993 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0); in goya_sw_init()
994 if (!hdev->dma_pool) { in goya_sw_init()
995 dev_err(hdev->dev, "failed to create DMA pool\n"); in goya_sw_init()
996 rc = -ENOMEM; in goya_sw_init()
1000 hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, in goya_sw_init()
1001 &hdev->cpu_accessible_dma_address, in goya_sw_init()
1004 if (!hdev->cpu_accessible_dma_mem) { in goya_sw_init()
1005 rc = -ENOMEM; in goya_sw_init()
1009 dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n", in goya_sw_init()
1010 &hdev->cpu_accessible_dma_address); in goya_sw_init()
1012 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1); in goya_sw_init()
1013 if (!hdev->cpu_accessible_dma_pool) { in goya_sw_init()
1014 dev_err(hdev->dev, in goya_sw_init()
1016 rc = -ENOMEM; in goya_sw_init()
1020 rc = gen_pool_add(hdev->cpu_accessible_dma_pool, in goya_sw_init()
1021 (uintptr_t) hdev->cpu_accessible_dma_mem, in goya_sw_init()
1022 HL_CPU_ACCESSIBLE_MEM_SIZE, -1); in goya_sw_init()
1024 dev_err(hdev->dev, in goya_sw_init()
1026 rc = -EFAULT; in goya_sw_init()
1030 spin_lock_init(&goya->hw_queues_lock); in goya_sw_init()
1031 hdev->supports_coresight = true; in goya_sw_init()
1032 hdev->asic_prop.supports_compute_reset = true; in goya_sw_init()
1033 hdev->asic_prop.allow_inference_soft_reset = true; in goya_sw_init()
1034 hdev->supports_wait_for_multi_cs = false; in goya_sw_init()
1035 hdev->supports_ctx_switch = true; in goya_sw_init()
1037 hdev->asic_funcs->set_pci_memory_regions(hdev); in goya_sw_init()
1039 goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL); in goya_sw_init()
1040 if (!goya->goya_work) { in goya_sw_init()
1041 rc = -ENOMEM; in goya_sw_init()
1045 goya->goya_work->hdev = hdev; in goya_sw_init()
1046 INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job); in goya_sw_init()
1051 gen_pool_destroy(hdev->cpu_accessible_dma_pool); in goya_sw_init()
1053 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, in goya_sw_init()
1054 hdev->cpu_accessible_dma_address); in goya_sw_init()
1056 dma_pool_destroy(hdev->dma_pool); in goya_sw_init()
1064 * goya_sw_fini - Goya software tear-down code
1071 struct goya_device *goya = hdev->asic_specific; in goya_sw_fini()
1073 gen_pool_destroy(hdev->cpu_accessible_dma_pool); in goya_sw_fini()
1075 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, in goya_sw_fini()
1076 hdev->cpu_accessible_dma_address); in goya_sw_fini()
1078 dma_pool_destroy(hdev->dma_pool); in goya_sw_fini()
1080 kfree(goya->goya_work); in goya_sw_fini()
1089 struct goya_device *goya = hdev->asic_specific; in goya_init_dma_qman()
1093 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman()
1126 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_init_dma_qman()
1131 if (hdev->stop_on_err) in goya_init_dma_qman()
1142 u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1); in goya_init_dma_ch()
1156 (dma_id - 1) * 4; in goya_init_dma_ch()
1165 * goya_init_dma_qmans - Initialize QMAN DMA registers
1174 struct goya_device *goya = hdev->asic_specific; in goya_init_dma_qmans()
1178 if (goya->hw_cap_initialized & HW_CAP_DMA) in goya_init_dma_qmans()
1181 q = &hdev->kernel_queues[0]; in goya_init_dma_qmans()
1184 q->cq_id = q->msi_vec = i; in goya_init_dma_qmans()
1185 goya_init_dma_qman(hdev, i, q->bus_address); in goya_init_dma_qmans()
1189 goya->hw_cap_initialized |= HW_CAP_DMA; in goya_init_dma_qmans()
1193 * goya_disable_external_queues - Disable external queues
1200 struct goya_device *goya = hdev->asic_specific; in goya_disable_external_queues()
1202 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) in goya_disable_external_queues()
1246 dev_err(hdev->dev, in goya_stop_queue()
1248 return -EINVAL; in goya_stop_queue()
1255 * goya_stop_external_queues - Stop external queues
1266 struct goya_device *goya = hdev->asic_specific; in goya_stop_external_queues()
1268 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) in goya_stop_external_queues()
1277 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n"); in goya_stop_external_queues()
1278 retval = -EIO; in goya_stop_external_queues()
1287 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n"); in goya_stop_external_queues()
1288 retval = -EIO; in goya_stop_external_queues()
1297 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n"); in goya_stop_external_queues()
1298 retval = -EIO; in goya_stop_external_queues()
1307 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n"); in goya_stop_external_queues()
1308 retval = -EIO; in goya_stop_external_queues()
1317 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n"); in goya_stop_external_queues()
1318 retval = -EIO; in goya_stop_external_queues()
1325 * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1334 struct goya_device *goya = hdev->asic_specific; in goya_init_cpu_queues()
1335 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_init_cpu_queues()
1338 struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; in goya_init_cpu_queues()
1341 if (!hdev->cpu_queues_enable) in goya_init_cpu_queues()
1344 if (goya->hw_cap_initialized & HW_CAP_CPU_Q) in goya_init_cpu_queues()
1347 eq = &hdev->event_queue; in goya_init_cpu_queues()
1349 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); in goya_init_cpu_queues()
1350 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); in goya_init_cpu_queues()
1352 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); in goya_init_cpu_queues()
1353 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); in goya_init_cpu_queues()
1383 dev_err(hdev->dev, in goya_init_cpu_queues()
1385 return -EIO; in goya_init_cpu_queues()
1389 if (prop->fw_cpu_boot_dev_sts0_valid) in goya_init_cpu_queues()
1390 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0); in goya_init_cpu_queues()
1392 if (prop->fw_cpu_boot_dev_sts1_valid) in goya_init_cpu_queues()
1393 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1); in goya_init_cpu_queues()
1395 goya->hw_cap_initialized |= HW_CAP_CPU_Q; in goya_init_cpu_queues()
1451 tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE); in _goya_tpc_mbist_workaround()
1461 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n", in _goya_tpc_mbist_workaround()
1489 dev_err(hdev->dev, in _goya_tpc_mbist_workaround()
1510 struct goya_device *goya = hdev->asic_specific; in goya_tpc_mbist_workaround()
1513 if (hdev->pldm) in goya_tpc_mbist_workaround()
1516 if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST) in goya_tpc_mbist_workaround()
1524 goya->hw_cap_initialized |= HW_CAP_TPC_MBIST; in goya_tpc_mbist_workaround()
1528 * goya_init_golden_registers - Initialize golden registers
1537 struct goya_device *goya = hdev->asic_specific; in goya_init_golden_registers()
1541 if (goya->hw_cap_initialized & HW_CAP_GOLDEN) in goya_init_golden_registers()
1817 * Workaround for H2 #HW-23 bug in goya_init_golden_registers()
1818 * Set DMA max outstanding read requests to 240 on DMA CH 1. in goya_init_golden_registers()
1827 goya->hw_cap_initialized |= HW_CAP_GOLDEN; in goya_init_golden_registers()
1847 qman_base_addr = hdev->asic_prop.sram_base_address + in goya_init_mme_qman()
1918 struct goya_device *goya = hdev->asic_specific; in goya_init_mme_qmans()
1921 if (goya->hw_cap_initialized & HW_CAP_MME) in goya_init_mme_qmans()
1933 goya->hw_cap_initialized |= HW_CAP_MME; in goya_init_mme_qmans()
1942 u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI); in goya_init_tpc_qman()
1954 qman_base_addr = hdev->asic_prop.sram_base_address + base_off; in goya_init_tpc_qman()
1991 u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1); in goya_init_tpc_cmdq()
2025 struct goya_device *goya = hdev->asic_specific; in goya_init_tpc_qmans()
2027 u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW - in goya_init_tpc_qmans()
2031 if (goya->hw_cap_initialized & HW_CAP_TPC) in goya_init_tpc_qmans()
2056 goya->hw_cap_initialized |= HW_CAP_TPC; in goya_init_tpc_qmans()
2060 * goya_disable_internal_queues - Disable internal queues
2067 struct goya_device *goya = hdev->asic_specific; in goya_disable_internal_queues()
2069 if (!(goya->hw_cap_initialized & HW_CAP_MME)) in goya_disable_internal_queues()
2076 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) in goya_disable_internal_queues()
2105 * goya_stop_internal_queues - Stop internal queues
2114 struct goya_device *goya = hdev->asic_specific; in goya_stop_internal_queues()
2117 if (!(goya->hw_cap_initialized & HW_CAP_MME)) in goya_stop_internal_queues()
2132 dev_err(hdev->dev, "failed to stop MME QMAN\n"); in goya_stop_internal_queues()
2133 retval = -EIO; in goya_stop_internal_queues()
2142 dev_err(hdev->dev, "failed to stop MME CMDQ\n"); in goya_stop_internal_queues()
2143 retval = -EIO; in goya_stop_internal_queues()
2147 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) in goya_stop_internal_queues()
2156 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n"); in goya_stop_internal_queues()
2157 retval = -EIO; in goya_stop_internal_queues()
2166 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n"); in goya_stop_internal_queues()
2167 retval = -EIO; in goya_stop_internal_queues()
2176 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n"); in goya_stop_internal_queues()
2177 retval = -EIO; in goya_stop_internal_queues()
2186 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n"); in goya_stop_internal_queues()
2187 retval = -EIO; in goya_stop_internal_queues()
2196 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n"); in goya_stop_internal_queues()
2197 retval = -EIO; in goya_stop_internal_queues()
2206 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n"); in goya_stop_internal_queues()
2207 retval = -EIO; in goya_stop_internal_queues()
2216 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n"); in goya_stop_internal_queues()
2217 retval = -EIO; in goya_stop_internal_queues()
2226 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n"); in goya_stop_internal_queues()
2227 retval = -EIO; in goya_stop_internal_queues()
2236 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n"); in goya_stop_internal_queues()
2237 retval = -EIO; in goya_stop_internal_queues()
2246 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n"); in goya_stop_internal_queues()
2247 retval = -EIO; in goya_stop_internal_queues()
2256 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n"); in goya_stop_internal_queues()
2257 retval = -EIO; in goya_stop_internal_queues()
2266 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n"); in goya_stop_internal_queues()
2267 retval = -EIO; in goya_stop_internal_queues()
2276 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n"); in goya_stop_internal_queues()
2277 retval = -EIO; in goya_stop_internal_queues()
2286 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n"); in goya_stop_internal_queues()
2287 retval = -EIO; in goya_stop_internal_queues()
2296 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n"); in goya_stop_internal_queues()
2297 retval = -EIO; in goya_stop_internal_queues()
2306 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n"); in goya_stop_internal_queues()
2307 retval = -EIO; in goya_stop_internal_queues()
2315 struct goya_device *goya = hdev->asic_specific; in goya_dma_stall()
2317 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) in goya_dma_stall()
2329 struct goya_device *goya = hdev->asic_specific; in goya_tpc_stall()
2331 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) in goya_tpc_stall()
2346 struct goya_device *goya = hdev->asic_specific; in goya_mme_stall()
2348 if (!(goya->hw_cap_initialized & HW_CAP_MME)) in goya_mme_stall()
2356 struct goya_device *goya = hdev->asic_specific; in goya_enable_msix()
2357 int cq_cnt = hdev->asic_prop.completion_queues_count; in goya_enable_msix()
2360 if (goya->hw_cap_initialized & HW_CAP_MSIX) in goya_enable_msix()
2363 rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES, in goya_enable_msix()
2366 dev_err(hdev->dev, in goya_enable_msix()
2367 "MSI-X: Failed to enable support -- %d/%d\n", in goya_enable_msix()
2373 irq = pci_irq_vector(hdev->pdev, i); in goya_enable_msix()
2375 &hdev->completion_queue[i]); in goya_enable_msix()
2377 dev_err(hdev->dev, "Failed to request IRQ %d", irq); in goya_enable_msix()
2382 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX); in goya_enable_msix()
2386 &hdev->event_queue); in goya_enable_msix()
2388 dev_err(hdev->dev, "Failed to request IRQ %d", irq); in goya_enable_msix()
2392 goya->hw_cap_initialized |= HW_CAP_MSIX; in goya_enable_msix()
2397 free_irq(pci_irq_vector(hdev->pdev, i), in goya_enable_msix()
2398 &hdev->completion_queue[i]); in goya_enable_msix()
2400 pci_free_irq_vectors(hdev->pdev); in goya_enable_msix()
2406 struct goya_device *goya = hdev->asic_specific; in goya_sync_irqs()
2409 if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) in goya_sync_irqs()
2413 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) in goya_sync_irqs()
2414 synchronize_irq(pci_irq_vector(hdev->pdev, i)); in goya_sync_irqs()
2416 synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX)); in goya_sync_irqs()
2421 struct goya_device *goya = hdev->asic_specific; in goya_disable_msix()
2424 if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) in goya_disable_msix()
2429 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX); in goya_disable_msix()
2430 free_irq(irq, &hdev->event_queue); in goya_disable_msix()
2432 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) { in goya_disable_msix()
2433 irq = pci_irq_vector(hdev->pdev, i); in goya_disable_msix()
2434 free_irq(irq, &hdev->completion_queue[i]); in goya_disable_msix()
2437 pci_free_irq_vectors(hdev->pdev); in goya_disable_msix()
2439 goya->hw_cap_initialized &= ~HW_CAP_MSIX; in goya_disable_msix()
2445 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); in goya_enable_timestamp()
2447 /* Zero the lower/upper parts of the 64-bit counter */ in goya_enable_timestamp()
2448 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); in goya_enable_timestamp()
2449 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); in goya_enable_timestamp()
2452 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); in goya_enable_timestamp()
2458 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); in goya_disable_timestamp()
2465 if (hdev->pldm) in goya_halt_engines()
2495 * goya_load_firmware_to_device() - Load LINUX FW code to device.
2500 * Return: 0 on success, non-zero for failure.
2506 dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; in goya_load_firmware_to_device()
2512 * goya_load_boot_fit_to_device() - Load boot fit to device.
2517 * Return: 0 on success, non-zero for failure.
2523 dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET; in goya_load_boot_fit_to_device()
2533 dynamic_loader = &hdev->fw_loader.dynamic_loader; in goya_init_dynamic_firmware_loader()
2538 * hard-coded) in later stages of the protocol those values will be in goya_init_dynamic_firmware_loader()
2540 * will always be up-to-date in goya_init_dynamic_firmware_loader()
2542 dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs; in goya_init_dynamic_firmware_loader()
2543 dyn_regs->kmd_msg_to_cpu = in goya_init_dynamic_firmware_loader()
2545 dyn_regs->cpu_cmd_status_to_host = in goya_init_dynamic_firmware_loader()
2548 dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC; in goya_init_dynamic_firmware_loader()
2555 static_loader = &hdev->fw_loader.static_loader; in goya_init_static_firmware_loader()
2557 static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN; in goya_init_static_firmware_loader()
2558 static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN; in goya_init_static_firmware_loader()
2559 static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU; in goya_init_static_firmware_loader()
2560 static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST; in goya_init_static_firmware_loader()
2561 static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; in goya_init_static_firmware_loader()
2562 static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0; in goya_init_static_firmware_loader()
2563 static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1; in goya_init_static_firmware_loader()
2564 static_loader->boot_err0_reg = mmCPU_BOOT_ERR0; in goya_init_static_firmware_loader()
2565 static_loader->boot_err1_reg = mmCPU_BOOT_ERR1; in goya_init_static_firmware_loader()
2566 static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET; in goya_init_static_firmware_loader()
2567 static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET; in goya_init_static_firmware_loader()
2568 static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR)); in goya_init_static_firmware_loader()
2573 struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; in goya_init_firmware_preload_params()
2575 pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; in goya_init_firmware_preload_params()
2576 pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0; in goya_init_firmware_preload_params()
2577 pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1; in goya_init_firmware_preload_params()
2578 pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0; in goya_init_firmware_preload_params()
2579 pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1; in goya_init_firmware_preload_params()
2580 pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; in goya_init_firmware_preload_params()
2585 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_init_firmware_loader()
2586 struct fw_load_mgr *fw_loader = &hdev->fw_loader; in goya_init_firmware_loader()
2589 fw_loader->fw_comp_loaded = FW_TYPE_NONE; in goya_init_firmware_loader()
2590 fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE; in goya_init_firmware_loader()
2591 fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE; in goya_init_firmware_loader()
2592 fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC; in goya_init_firmware_loader()
2593 fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; in goya_init_firmware_loader()
2594 fw_loader->skip_bmc = false; in goya_init_firmware_loader()
2595 fw_loader->sram_bar_id = SRAM_CFG_BAR_ID; in goya_init_firmware_loader()
2596 fw_loader->dram_bar_id = DDR_BAR_ID; in goya_init_firmware_loader()
2598 if (prop->dynamic_fw_load) in goya_init_firmware_loader()
2606 struct goya_device *goya = hdev->asic_specific; in goya_init_cpu()
2609 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU)) in goya_init_cpu()
2612 if (goya->hw_cap_initialized & HW_CAP_CPU) in goya_init_cpu()
2616 * Before pushing u-boot/linux to device, need to set the ddr bar to in goya_init_cpu()
2620 dev_err(hdev->dev, in goya_init_cpu()
2622 return -EIO; in goya_init_cpu()
2630 goya->hw_cap_initialized |= HW_CAP_CPU; in goya_init_cpu()
2641 if (hdev->pldm) in goya_mmu_update_asid_hop0_addr()
2659 dev_err(hdev->dev, in goya_mmu_update_asid_hop0_addr()
2669 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_init()
2670 struct goya_device *goya = hdev->asic_specific; in goya_mmu_init()
2674 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_mmu_init()
2677 hdev->dram_default_page_mapping = true; in goya_mmu_init()
2679 for (i = 0 ; i < prop->max_asid ; i++) { in goya_mmu_init()
2680 hop0_addr = prop->mmu_pgt_addr + in goya_mmu_init()
2681 (i * prop->mmu_hop_table_size); in goya_mmu_init()
2685 dev_err(hdev->dev, in goya_mmu_init()
2691 goya->hw_cap_initialized |= HW_CAP_MMU; in goya_mmu_init()
2714 * goya_hw_init - Goya hardware initialization code
2723 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_hw_init()
2739 dev_err(hdev->dev, "failed to initialize CPU\n"); in goya_hw_init()
2752 ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) { in goya_hw_init()
2753 dev_err(hdev->dev, in goya_hw_init()
2755 return -EIO; in goya_hw_init()
2772 /* MSI-X must be enabled before CPU queues are initialized */ in goya_hw_init()
2777 /* Perform read from the device to flush all MSI-X configuration */ in goya_hw_init()
2791 struct goya_device *goya = hdev->asic_specific; in goya_hw_fini()
2794 if (hdev->pldm) { in goya_hw_fini()
2817 dev_dbg(hdev->dev, in goya_hw_fini()
2822 dev_dbg(hdev->dev, in goya_hw_fini()
2836 dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status); in goya_hw_fini()
2837 return -ETIMEDOUT; in goya_hw_fini()
2841 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME | in goya_hw_fini()
2848 /* Chicken bit to re-initiate boot sequencer flow */ in goya_hw_fini()
2856 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | in goya_hw_fini()
2862 memset(goya->events_stat, 0, sizeof(goya->events_stat)); in goya_hw_fini()
2873 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); in goya_suspend()
2891 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, in goya_mmap()
2892 (dma_addr - HOST_PHYS_BASE), size); in goya_mmap()
2894 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc); in goya_mmap()
2966 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n", in goya_ring_doorbell()
2993 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size, in goya_dma_alloc_coherent()
3007 dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE; in goya_dma_free_coherent()
3009 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); in goya_dma_free_coherent()
3023 *dma_handle = hdev->asic_prop.sram_base_address; in goya_get_int_queue_base()
3025 base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID]; in goya_get_int_queue_base()
3065 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id); in goya_get_int_queue_base()
3084 if (hdev->pldm) in goya_send_job_on_qman0()
3089 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) { in goya_send_job_on_qman0()
3090 dev_err_ratelimited(hdev->dev, in goya_send_job_on_qman0()
3092 return -EBUSY; in goya_send_job_on_qman0()
3097 dev_err(hdev->dev, in goya_send_job_on_qman0()
3099 return -ENOMEM; in goya_send_job_on_qman0()
3104 cb = job->patched_cb; in goya_send_job_on_qman0()
3106 fence_pkt = cb->kernel_address + in goya_send_job_on_qman0()
3107 job->job_cb_size - sizeof(struct packet_msg_prot); in goya_send_job_on_qman0()
3112 fence_pkt->ctl = cpu_to_le32(tmp); in goya_send_job_on_qman0()
3113 fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL); in goya_send_job_on_qman0()
3114 fence_pkt->addr = cpu_to_le64(fence_dma_addr); in goya_send_job_on_qman0()
3117 job->job_cb_size, cb->bus_address); in goya_send_job_on_qman0()
3119 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc); in goya_send_job_on_qman0()
3129 if (rc == -ETIMEDOUT) { in goya_send_job_on_qman0()
3130 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp); in goya_send_job_on_qman0()
3145 struct goya_device *goya = hdev->asic_specific; in goya_send_cpu_message()
3147 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) { in goya_send_cpu_message()
3173 dev_err(hdev->dev, in goya_test_queue()
3176 return -ENOMEM; in goya_test_queue()
3184 dev_err(hdev->dev, in goya_test_queue()
3187 rc = -ENOMEM; in goya_test_queue()
3194 fence_pkt->ctl = cpu_to_le32(tmp); in goya_test_queue()
3195 fence_pkt->value = cpu_to_le32(fence_val); in goya_test_queue()
3196 fence_pkt->addr = cpu_to_le64(fence_dma_addr); in goya_test_queue()
3202 dev_err(hdev->dev, in goya_test_queue()
3213 if (rc == -ETIMEDOUT) { in goya_test_queue()
3214 dev_err(hdev->dev, in goya_test_queue()
3217 rc = -EIO; in goya_test_queue()
3229 struct goya_device *goya = hdev->asic_specific; in goya_test_cpu_queue()
3235 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_test_cpu_queue()
3248 ret_val = -EINVAL; in goya_test_queues()
3262 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); in goya_dma_pool_zalloc()
3275 dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE; in goya_dma_pool_free()
3277 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr); in goya_dma_pool_free()
3286 *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address + in goya_cpu_accessible_dma_pool_alloc()
3314 while ((count + 1) < sgt->nents) { in goya_get_dma_desc_list_size()
3346 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), in goya_pin_memory_before_cs()
3347 parser->job_userptr_list, &userptr)) in goya_pin_memory_before_cs()
3352 return -ENOMEM; in goya_pin_memory_before_cs()
3354 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), in goya_pin_memory_before_cs()
3359 list_add_tail(&userptr->job_node, parser->job_userptr_list); in goya_pin_memory_before_cs()
3361 rc = hdev->asic_funcs->asic_dma_map_sgtable(hdev, userptr->sgt, dir); in goya_pin_memory_before_cs()
3363 dev_err(hdev->dev, "failed to map sgt with DMA region\n"); in goya_pin_memory_before_cs()
3367 userptr->dma_mapped = true; in goya_pin_memory_before_cs()
3368 userptr->dir = dir; in goya_pin_memory_before_cs()
3371 parser->patched_cb_size += in goya_pin_memory_before_cs()
3372 goya_get_dma_desc_list_size(hdev, userptr->sgt); in goya_pin_memory_before_cs()
3377 list_del(&userptr->job_node); in goya_pin_memory_before_cs()
3397 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_validate_dma_pkt_host()
3407 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n"); in goya_validate_dma_pkt_host()
3410 addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3411 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3417 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n"); in goya_validate_dma_pkt_host()
3420 addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3421 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3425 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n"); in goya_validate_dma_pkt_host()
3427 addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3428 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3434 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n"); in goya_validate_dma_pkt_host()
3436 addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3437 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3440 dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir); in goya_validate_dma_pkt_host()
3441 return -EFAULT; in goya_validate_dma_pkt_host()
3446 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_host()
3447 hdev->asic_prop.sram_user_base_address, in goya_validate_dma_pkt_host()
3448 hdev->asic_prop.sram_end_address)) { in goya_validate_dma_pkt_host()
3450 dev_err(hdev->dev, in goya_validate_dma_pkt_host()
3453 user_dma_pkt->tsize); in goya_validate_dma_pkt_host()
3454 return -EFAULT; in goya_validate_dma_pkt_host()
3458 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_host()
3459 hdev->asic_prop.dram_user_base_address, in goya_validate_dma_pkt_host()
3460 hdev->asic_prop.dram_end_address)) { in goya_validate_dma_pkt_host()
3462 dev_err(hdev->dev, in goya_validate_dma_pkt_host()
3465 user_dma_pkt->tsize); in goya_validate_dma_pkt_host()
3466 return -EFAULT; in goya_validate_dma_pkt_host()
3471 parser->patched_cb_size += sizeof(*user_dma_pkt); in goya_validate_dma_pkt_host()
3474 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) { in goya_validate_dma_pkt_host()
3475 dev_err(hdev->dev, in goya_validate_dma_pkt_host()
3477 return -EFAULT; in goya_validate_dma_pkt_host()
3495 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_validate_dma_pkt_no_host()
3500 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n"); in goya_validate_dma_pkt_no_host()
3501 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_no_host()
3502 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_no_host()
3504 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n"); in goya_validate_dma_pkt_no_host()
3505 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_no_host()
3506 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_no_host()
3510 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_no_host()
3511 hdev->asic_prop.sram_user_base_address, in goya_validate_dma_pkt_no_host()
3512 hdev->asic_prop.sram_end_address)) { in goya_validate_dma_pkt_no_host()
3513 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n", in goya_validate_dma_pkt_no_host()
3514 sram_memory_addr, user_dma_pkt->tsize); in goya_validate_dma_pkt_no_host()
3515 return -EFAULT; in goya_validate_dma_pkt_no_host()
3519 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_no_host()
3520 hdev->asic_prop.dram_user_base_address, in goya_validate_dma_pkt_no_host()
3521 hdev->asic_prop.dram_end_address)) { in goya_validate_dma_pkt_no_host()
3522 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n", in goya_validate_dma_pkt_no_host()
3523 dram_memory_addr, user_dma_pkt->tsize); in goya_validate_dma_pkt_no_host()
3524 return -EFAULT; in goya_validate_dma_pkt_no_host()
3527 parser->patched_cb_size += sizeof(*user_dma_pkt); in goya_validate_dma_pkt_no_host()
3540 dev_dbg(hdev->dev, "DMA packet details:\n"); in goya_validate_dma_pkt_no_mmu()
3541 dev_dbg(hdev->dev, "source == 0x%llx\n", in goya_validate_dma_pkt_no_mmu()
3542 le64_to_cpu(user_dma_pkt->src_addr)); in goya_validate_dma_pkt_no_mmu()
3543 dev_dbg(hdev->dev, "destination == 0x%llx\n", in goya_validate_dma_pkt_no_mmu()
3544 le64_to_cpu(user_dma_pkt->dst_addr)); in goya_validate_dma_pkt_no_mmu()
3545 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); in goya_validate_dma_pkt_no_mmu()
3547 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_validate_dma_pkt_no_mmu()
3555 if (user_dma_pkt->tsize == 0) { in goya_validate_dma_pkt_no_mmu()
3556 dev_err(hdev->dev, in goya_validate_dma_pkt_no_mmu()
3558 return -EINVAL; in goya_validate_dma_pkt_no_mmu()
3573 dev_dbg(hdev->dev, "DMA packet details:\n"); in goya_validate_dma_pkt_mmu()
3574 dev_dbg(hdev->dev, "source == 0x%llx\n", in goya_validate_dma_pkt_mmu()
3575 le64_to_cpu(user_dma_pkt->src_addr)); in goya_validate_dma_pkt_mmu()
3576 dev_dbg(hdev->dev, "destination == 0x%llx\n", in goya_validate_dma_pkt_mmu()
3577 le64_to_cpu(user_dma_pkt->dst_addr)); in goya_validate_dma_pkt_mmu()
3578 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); in goya_validate_dma_pkt_mmu()
3581 * WA for HW-23. in goya_validate_dma_pkt_mmu()
3585 if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 && in goya_validate_dma_pkt_mmu()
3586 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr), in goya_validate_dma_pkt_mmu()
3587 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_mmu()
3588 hdev->asic_prop.pmmu.start_addr, in goya_validate_dma_pkt_mmu()
3589 hdev->asic_prop.pmmu.end_addr)) { in goya_validate_dma_pkt_mmu()
3590 dev_err(hdev->dev, in goya_validate_dma_pkt_mmu()
3592 return -EFAULT; in goya_validate_dma_pkt_mmu()
3595 if (user_dma_pkt->tsize == 0) { in goya_validate_dma_pkt_mmu()
3596 dev_err(hdev->dev, in goya_validate_dma_pkt_mmu()
3598 return -EINVAL; in goya_validate_dma_pkt_mmu()
3601 parser->patched_cb_size += sizeof(*user_dma_pkt); in goya_validate_dma_pkt_mmu()
3610 struct goya_device *goya = hdev->asic_specific; in goya_validate_wreg32()
3614 reg_offset = le32_to_cpu(wreg_pkt->ctl) & in goya_validate_wreg32()
3617 dev_dbg(hdev->dev, "WREG32 packet details:\n"); in goya_validate_wreg32()
3618 dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset); in goya_validate_wreg32()
3619 dev_dbg(hdev->dev, "value == 0x%x\n", in goya_validate_wreg32()
3620 le32_to_cpu(wreg_pkt->value)); in goya_validate_wreg32()
3623 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n", in goya_validate_wreg32()
3625 return -EPERM; in goya_validate_wreg32()
3631 * non-secured property in goya_validate_wreg32()
3633 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_validate_wreg32()
3639 if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) || in goya_validate_wreg32()
3640 (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) { in goya_validate_wreg32()
3642 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n", in goya_validate_wreg32()
3643 wreg_pkt->value); in goya_validate_wreg32()
3644 return -EPERM; in goya_validate_wreg32()
3656 parser->patched_cb_size = 0; in goya_validate_cb()
3659 while (cb_parsed_length < parser->user_cb_size) { in goya_validate_cb()
3664 user_pkt = parser->user_cb->kernel_address + cb_parsed_length; in goya_validate_cb()
3667 (le64_to_cpu(user_pkt->header) & in goya_validate_cb()
3672 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id); in goya_validate_cb()
3673 rc = -EINVAL; in goya_validate_cb()
3679 if (cb_parsed_length > parser->user_cb_size) { in goya_validate_cb()
3680 dev_err(hdev->dev, in goya_validate_cb()
3682 rc = -EINVAL; in goya_validate_cb()
3695 parser->patched_cb_size += pkt_size; in goya_validate_cb()
3699 dev_err(hdev->dev, in goya_validate_cb()
3701 rc = -EPERM; in goya_validate_cb()
3705 dev_err(hdev->dev, in goya_validate_cb()
3707 rc = -EPERM; in goya_validate_cb()
3711 dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); in goya_validate_cb()
3712 rc = -EPERM; in goya_validate_cb()
3716 dev_err(hdev->dev, "User not allowed to use STOP\n"); in goya_validate_cb()
3717 rc = -EPERM; in goya_validate_cb()
3733 parser->patched_cb_size += pkt_size; in goya_validate_cb()
3737 dev_err(hdev->dev, "Invalid packet header 0x%x\n", in goya_validate_cb()
3739 rc = -EINVAL; in goya_validate_cb()
3750 * 2. A packet that will generate MSI-X interrupt in goya_validate_cb()
3752 parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; in goya_validate_cb()
3776 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_patch_dma_packet()
3785 (user_dma_pkt->tsize == 0)) { in goya_patch_dma_packet()
3792 addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_patch_dma_packet()
3793 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_patch_dma_packet()
3798 addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_patch_dma_packet()
3799 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_patch_dma_packet()
3805 le32_to_cpu(user_dma_pkt->tsize), in goya_patch_dma_packet()
3806 parser->job_userptr_list, &userptr) == false)) { in goya_patch_dma_packet()
3807 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n", in goya_patch_dma_packet()
3808 addr, user_dma_pkt->tsize); in goya_patch_dma_packet()
3809 return -EFAULT; in goya_patch_dma_packet()
3822 sgt = userptr->sgt; in goya_patch_dma_packet()
3832 while ((count + 1) < sgt->nents) { in goya_patch_dma_packet()
3850 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_patch_dma_packet()
3855 new_dma_pkt->ctl = cpu_to_le32(ctl); in goya_patch_dma_packet()
3856 new_dma_pkt->tsize = cpu_to_le32((u32) len); in goya_patch_dma_packet()
3859 new_dma_pkt->src_addr = cpu_to_le64(dma_addr); in goya_patch_dma_packet()
3860 new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr); in goya_patch_dma_packet()
3862 new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr); in goya_patch_dma_packet()
3863 new_dma_pkt->dst_addr = cpu_to_le64(dma_addr); in goya_patch_dma_packet()
3873 dev_err(hdev->dev, in goya_patch_dma_packet()
3875 return -EFAULT; in goya_patch_dma_packet()
3878 /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */ in goya_patch_dma_packet()
3879 new_dma_pkt--; in goya_patch_dma_packet()
3880 new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask); in goya_patch_dma_packet()
3895 while (cb_parsed_length < parser->user_cb_size) { in goya_patch_cb()
3901 user_pkt = parser->user_cb->kernel_address + cb_parsed_length; in goya_patch_cb()
3902 kernel_pkt = parser->patched_cb->kernel_address + in goya_patch_cb()
3906 (le64_to_cpu(user_pkt->header) & in goya_patch_cb()
3911 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id); in goya_patch_cb()
3912 rc = -EINVAL; in goya_patch_cb()
3918 if (cb_parsed_length > parser->user_cb_size) { in goya_patch_cb()
3919 dev_err(hdev->dev, in goya_patch_cb()
3921 rc = -EINVAL; in goya_patch_cb()
3942 dev_err(hdev->dev, in goya_patch_cb()
3944 rc = -EPERM; in goya_patch_cb()
3948 dev_err(hdev->dev, in goya_patch_cb()
3950 rc = -EPERM; in goya_patch_cb()
3954 dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); in goya_patch_cb()
3955 rc = -EPERM; in goya_patch_cb()
3959 dev_err(hdev->dev, "User not allowed to use STOP\n"); in goya_patch_cb()
3960 rc = -EPERM; in goya_patch_cb()
3972 dev_err(hdev->dev, "Invalid packet header 0x%x\n", in goya_patch_cb()
3974 rc = -EINVAL; in goya_patch_cb()
3996 * 2. A packet that will generate MSI-X interrupt in goya_parse_cb_mmu()
3998 parser->patched_cb_size = parser->user_cb_size + in goya_parse_cb_mmu()
4001 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, in goya_parse_cb_mmu()
4002 parser->patched_cb_size, false, false, in goya_parse_cb_mmu()
4006 dev_err(hdev->dev, in goya_parse_cb_mmu()
4012 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_mmu()
4014 if (!parser->patched_cb) { in goya_parse_cb_mmu()
4015 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle); in goya_parse_cb_mmu()
4016 rc = -EFAULT; in goya_parse_cb_mmu()
4021 * The check that parser->user_cb_size <= parser->user_cb->size was done in goya_parse_cb_mmu()
4024 memcpy(parser->patched_cb->kernel_address, in goya_parse_cb_mmu()
4025 parser->user_cb->kernel_address, in goya_parse_cb_mmu()
4026 parser->user_cb_size); in goya_parse_cb_mmu()
4028 patched_cb_size = parser->patched_cb_size; in goya_parse_cb_mmu()
4031 user_cb = parser->user_cb; in goya_parse_cb_mmu()
4032 parser->user_cb = parser->patched_cb; in goya_parse_cb_mmu()
4034 parser->user_cb = user_cb; in goya_parse_cb_mmu()
4037 hl_cb_put(parser->patched_cb); in goya_parse_cb_mmu()
4041 if (patched_cb_size != parser->patched_cb_size) { in goya_parse_cb_mmu()
4042 dev_err(hdev->dev, "user CB size mismatch\n"); in goya_parse_cb_mmu()
4043 hl_cb_put(parser->patched_cb); in goya_parse_cb_mmu()
4044 rc = -EINVAL; in goya_parse_cb_mmu()
4055 hl_cb_destroy(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_mmu()
4071 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, in goya_parse_cb_no_mmu()
4072 parser->patched_cb_size, false, false, in goya_parse_cb_no_mmu()
4075 dev_err(hdev->dev, in goya_parse_cb_no_mmu()
4080 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_no_mmu()
4082 if (!parser->patched_cb) { in goya_parse_cb_no_mmu()
4083 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle); in goya_parse_cb_no_mmu()
4084 rc = -EFAULT; in goya_parse_cb_no_mmu()
4091 hl_cb_put(parser->patched_cb); in goya_parse_cb_no_mmu()
4100 hl_cb_destroy(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_no_mmu()
4104 hl_userptr_delete_list(hdev, parser->job_userptr_list); in goya_parse_cb_no_mmu()
4111 struct asic_fixed_properties *asic_prop = &hdev->asic_prop; in goya_parse_cb_no_ext_queue()
4112 struct goya_device *goya = hdev->asic_specific; in goya_parse_cb_no_ext_queue()
4114 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_parse_cb_no_ext_queue()
4119 (u64) (uintptr_t) parser->user_cb, in goya_parse_cb_no_ext_queue()
4120 parser->user_cb_size, in goya_parse_cb_no_ext_queue()
4121 asic_prop->sram_user_base_address, in goya_parse_cb_no_ext_queue()
4122 asic_prop->sram_end_address)) in goya_parse_cb_no_ext_queue()
4126 (u64) (uintptr_t) parser->user_cb, in goya_parse_cb_no_ext_queue()
4127 parser->user_cb_size, in goya_parse_cb_no_ext_queue()
4128 asic_prop->dram_user_base_address, in goya_parse_cb_no_ext_queue()
4129 asic_prop->dram_end_address)) in goya_parse_cb_no_ext_queue()
4132 dev_err(hdev->dev, in goya_parse_cb_no_ext_queue()
4134 parser->user_cb, parser->user_cb_size); in goya_parse_cb_no_ext_queue()
4136 return -EFAULT; in goya_parse_cb_no_ext_queue()
4141 struct goya_device *goya = hdev->asic_specific; in goya_cs_parser()
4143 if (parser->queue_type == QUEUE_TYPE_INT) in goya_cs_parser()
4146 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_cs_parser()
4159 cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2); in goya_add_end_of_cb_packets()
4164 cq_pkt->ctl = cpu_to_le32(tmp); in goya_add_end_of_cb_packets()
4165 cq_pkt->value = cpu_to_le32(cq_val); in goya_add_end_of_cb_packets()
4166 cq_pkt->addr = cpu_to_le64(cq_addr); in goya_add_end_of_cb_packets()
4172 cq_pkt->ctl = cpu_to_le32(tmp); in goya_add_end_of_cb_packets()
4173 cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF); in goya_add_end_of_cb_packets()
4174 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF); in goya_add_end_of_cb_packets()
4192 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4); in goya_clear_sm_regs()
4195 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4); in goya_clear_sm_regs()
4209 dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n"); in goya_debugfs_read_dma()
4210 return -EPERM; in goya_debugfs_read_dma()
4215 struct goya_device *goya = hdev->asic_specific; in goya_read_pte()
4217 if (hdev->reset_info.hard_reset_pending) in goya_read_pte()
4220 return readq(hdev->pcie_bar[DDR_BAR_ID] + in goya_read_pte()
4221 (addr - goya->ddr_bar_cur_addr)); in goya_read_pte()
4226 struct goya_device *goya = hdev->asic_specific; in goya_write_pte()
4228 if (hdev->reset_info.hard_reset_pending) in goya_write_pte()
4231 writeq(val, hdev->pcie_bar[DDR_BAR_ID] + in goya_write_pte()
4232 (addr - goya->ddr_bar_cur_addr)); in goya_write_pte()
4360 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3; in goya_get_event_desc()
4364 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0; in goya_get_event_desc()
4368 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0; in goya_get_event_desc()
4379 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3; in goya_get_event_desc()
4390 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10; in goya_get_event_desc()
4394 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ; in goya_get_event_desc()
4398 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM; in goya_get_event_desc()
4402 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM; in goya_get_event_desc()
4406 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH; in goya_get_event_desc()
4417 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10; in goya_get_event_desc()
4421 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0; in goya_get_event_desc()
4436 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n"); in goya_print_razwi_info()
4441 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n"); in goya_print_razwi_info()
4446 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n"); in goya_print_razwi_info()
4451 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n"); in goya_print_razwi_info()
4458 struct goya_device *goya = hdev->asic_specific; in goya_print_mmu_error_info()
4462 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_print_mmu_error_info()
4471 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n", in goya_print_mmu_error_info()
4481 struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; in goya_print_out_of_sync_info()
4483 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n", in goya_print_out_of_sync_info()
4484 le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci)); in goya_print_out_of_sync_info()
4493 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", in goya_print_irq_info()
4515 /* data should be aligned to 8 bytes in order to CPU-CP to copy it */ in goya_unmask_irq_arr()
4520 dev_err(hdev->dev, "too many elements in IRQ array\n"); in goya_unmask_irq_arr()
4521 return -EINVAL; in goya_unmask_irq_arr()
4526 return -ENOMEM; in goya_unmask_irq_arr()
4529 pkt->length = cpu_to_le32(irq_num_entries); in goya_unmask_irq_arr()
4534 for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs; in goya_unmask_irq_arr()
4539 pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << in goya_unmask_irq_arr()
4542 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, in goya_unmask_irq_arr()
4546 dev_err(hdev->dev, "failed to unmask IRQ array\n"); in goya_unmask_irq_arr()
4575 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), in goya_unmask_irq()
4579 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type); in goya_unmask_irq()
4588 mutex_lock(&hdev->clk_throttling.lock); in goya_print_clk_change_info()
4592 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER; in goya_print_clk_change_info()
4593 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER; in goya_print_clk_change_info()
4594 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get(); in goya_print_clk_change_info()
4595 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time; in goya_print_clk_change_info()
4596 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4601 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER; in goya_print_clk_change_info()
4602 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get(); in goya_print_clk_change_info()
4603 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4608 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL; in goya_print_clk_change_info()
4609 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL; in goya_print_clk_change_info()
4610 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get(); in goya_print_clk_change_info()
4611 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time; in goya_print_clk_change_info()
4612 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4617 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL; in goya_print_clk_change_info()
4618 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get(); in goya_print_clk_change_info()
4619 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4624 dev_err(hdev->dev, "Received invalid clock change event %d\n", in goya_print_clk_change_info()
4629 mutex_unlock(&hdev->clk_throttling.lock); in goya_print_clk_change_info()
4634 u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); in goya_handle_eqe()
4637 struct goya_device *goya = hdev->asic_specific; in goya_handle_eqe()
4640 dev_err(hdev->dev, "Event type %u exceeds maximum of %u", in goya_handle_eqe()
4641 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1); in goya_handle_eqe()
4645 goya->events_stat[event_type]++; in goya_handle_eqe()
4646 goya->events_stat_aggregate[event_type]++; in goya_handle_eqe()
4672 if (hdev->hard_reset_on_fw_events) in goya_handle_eqe()
4679 if (hdev->hard_reset_on_fw_events) in goya_handle_eqe()
4738 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err); in goya_handle_eqe()
4739 if (hdev->hard_reset_on_fw_events) in goya_handle_eqe()
4746 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n", in goya_handle_eqe()
4754 struct goya_device *goya = hdev->asic_specific; in goya_get_events_stat()
4757 *size = (u32) sizeof(goya->events_stat_aggregate); in goya_get_events_stat()
4758 return goya->events_stat_aggregate; in goya_get_events_stat()
4761 *size = (u32) sizeof(goya->events_stat); in goya_get_events_stat()
4762 return goya->events_stat; in goya_get_events_stat()
4779 return -ENOMEM; in goya_memset_device_memory()
4781 lin_dma_pkt = cb->kernel_address; in goya_memset_device_memory()
4793 lin_dma_pkt->ctl = cpu_to_le32(ctl); in goya_memset_device_memory()
4795 lin_dma_pkt->src_addr = cpu_to_le64(val); in goya_memset_device_memory()
4796 lin_dma_pkt->dst_addr = cpu_to_le64(addr); in goya_memset_device_memory()
4798 lin_dma_pkt->tsize = cpu_to_le32(SZ_2G); in goya_memset_device_memory()
4800 lin_dma_pkt->tsize = cpu_to_le32(size); in goya_memset_device_memory()
4802 size -= SZ_2G; in goya_memset_device_memory()
4805 } while (--lin_dma_pkts_cnt); in goya_memset_device_memory()
4809 dev_err(hdev->dev, "Failed to allocate a new job\n"); in goya_memset_device_memory()
4810 rc = -ENOMEM; in goya_memset_device_memory()
4814 job->id = 0; in goya_memset_device_memory()
4815 job->user_cb = cb; in goya_memset_device_memory()
4816 atomic_inc(&job->user_cb->cs_cnt); in goya_memset_device_memory()
4817 job->user_cb_size = cb_size; in goya_memset_device_memory()
4818 job->hw_queue_id = GOYA_QUEUE_ID_DMA_0; in goya_memset_device_memory()
4819 job->patched_cb = job->user_cb; in goya_memset_device_memory()
4820 job->job_cb_size = job->user_cb_size; in goya_memset_device_memory()
4828 atomic_dec(&cb->cs_cnt); in goya_memset_device_memory()
4832 hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle); in goya_memset_device_memory()
4839 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_context_switch()
4840 u64 addr = prop->sram_base_address, sob_addr; in goya_context_switch()
4841 u32 size = hdev->pldm ? 0x10000 : prop->sram_size; in goya_context_switch()
4844 u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO - in goya_context_switch()
4849 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n"); in goya_context_switch()
4859 (dma_id - 1) * 4; in goya_context_switch()
4873 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_clear_pgt_range()
4874 struct goya_device *goya = hdev->asic_specific; in goya_mmu_clear_pgt_range()
4875 u64 addr = prop->mmu_pgt_addr; in goya_mmu_clear_pgt_range()
4876 u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE + in goya_mmu_clear_pgt_range()
4879 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_clear_pgt_range()
4887 struct goya_device *goya = hdev->asic_specific; in goya_mmu_set_dram_default_page()
4888 u64 addr = hdev->asic_prop.mmu_dram_default_page_addr; in goya_mmu_set_dram_default_page()
4892 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_set_dram_default_page()
4900 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_add_mappings_for_device_cpu()
4901 struct goya_device *goya = hdev->asic_specific; in goya_mmu_add_mappings_for_device_cpu()
4905 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_add_mappings_for_device_cpu()
4909 rc = hl_mmu_map_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4910 prop->dram_base_address + off, in goya_mmu_add_mappings_for_device_cpu()
4911 prop->dram_base_address + off, PAGE_SIZE_2MB, in goya_mmu_add_mappings_for_device_cpu()
4914 dev_err(hdev->dev, "Map failed for address 0x%llx\n", in goya_mmu_add_mappings_for_device_cpu()
4915 prop->dram_base_address + off); in goya_mmu_add_mappings_for_device_cpu()
4920 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) { in goya_mmu_add_mappings_for_device_cpu()
4921 rc = hl_mmu_map_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4923 hdev->cpu_accessible_dma_address, in goya_mmu_add_mappings_for_device_cpu()
4927 dev_err(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4929 off -= PAGE_SIZE_2MB; in goya_mmu_add_mappings_for_device_cpu()
4934 rc = hl_mmu_map_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4936 hdev->cpu_accessible_dma_address + cpu_off, in goya_mmu_add_mappings_for_device_cpu()
4939 dev_err(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4941 cpu_off -= PAGE_SIZE_4KB; in goya_mmu_add_mappings_for_device_cpu()
4955 goya->device_cpu_mmu_mappings_done = true; in goya_mmu_add_mappings_for_device_cpu()
4960 for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB) in goya_mmu_add_mappings_for_device_cpu()
4961 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4964 dev_warn_ratelimited(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4968 for (; off >= 0 ; off -= PAGE_SIZE_2MB) in goya_mmu_add_mappings_for_device_cpu()
4969 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4970 prop->dram_base_address + off, PAGE_SIZE_2MB, in goya_mmu_add_mappings_for_device_cpu()
4972 dev_warn_ratelimited(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4974 prop->dram_base_address + off); in goya_mmu_add_mappings_for_device_cpu()
4981 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_remove_device_cpu_mappings()
4982 struct goya_device *goya = hdev->asic_specific; in goya_mmu_remove_device_cpu_mappings()
4985 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_remove_device_cpu_mappings()
4988 if (!goya->device_cpu_mmu_mappings_done) in goya_mmu_remove_device_cpu_mappings()
4994 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) { in goya_mmu_remove_device_cpu_mappings()
4995 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_remove_device_cpu_mappings()
4998 dev_warn(hdev->dev, in goya_mmu_remove_device_cpu_mappings()
5002 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_remove_device_cpu_mappings()
5006 dev_warn_ratelimited(hdev->dev, in goya_mmu_remove_device_cpu_mappings()
5012 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_remove_device_cpu_mappings()
5013 prop->dram_base_address + off, PAGE_SIZE_2MB, in goya_mmu_remove_device_cpu_mappings()
5015 dev_warn_ratelimited(hdev->dev, in goya_mmu_remove_device_cpu_mappings()
5017 prop->dram_base_address + off); in goya_mmu_remove_device_cpu_mappings()
5019 goya->device_cpu_mmu_mappings_done = false; in goya_mmu_remove_device_cpu_mappings()
5024 struct goya_device *goya = hdev->asic_specific; in goya_mmu_prepare()
5027 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_prepare()
5031 dev_crit(hdev->dev, "asid %u is too big\n", asid); in goya_mmu_prepare()
5043 struct goya_device *goya = hdev->asic_specific; in goya_mmu_invalidate_cache()
5047 if (!(goya->hw_cap_initialized & HW_CAP_MMU) || in goya_mmu_invalidate_cache()
5048 hdev->reset_info.hard_reset_pending) in goya_mmu_invalidate_cache()
5055 if (hdev->pldm) in goya_mmu_invalidate_cache()
5086 struct goya_device *goya = hdev->asic_specific; in goya_send_heartbeat()
5088 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_send_heartbeat()
5096 struct goya_device *goya = hdev->asic_specific; in goya_cpucp_info_get()
5097 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_cpucp_info_get()
5101 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_cpucp_info_get()
5110 dram_size = le64_to_cpu(prop->cpucp_info.dram_size); in goya_cpucp_info_get()
5114 dev_err(hdev->dev, in goya_cpucp_info_get()
5120 prop->dram_size = dram_size; in goya_cpucp_info_get()
5121 prop->dram_end_address = prop->dram_base_address + dram_size; in goya_cpucp_info_get()
5124 if (!strlen(prop->cpucp_info.card_name)) in goya_cpucp_info_get()
5125 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, in goya_cpucp_info_get()
5134 const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n"; in goya_is_device_idle()
5135 const char *dma_fmt = "%-5d%-9s%#-14x%#x\n"; in goya_is_device_idle()
5145 "--- ------- ------------ -------------\n"); in goya_is_device_idle()
5147 offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0; in goya_is_device_idle()
5166 "--- ------- ------------ -------------- ----------\n"); in goya_is_device_idle()
5168 offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0; in goya_is_device_idle()
5189 "--- ------- ------------ -------------- -----------\n"); in goya_is_device_idle()
5211 __acquires(&goya->hw_queues_lock) in goya_hw_queues_lock()
5213 struct goya_device *goya = hdev->asic_specific; in goya_hw_queues_lock()
5215 spin_lock(&goya->hw_queues_lock); in goya_hw_queues_lock()
5219 __releases(&goya->hw_queues_lock) in goya_hw_queues_unlock()
5221 struct goya_device *goya = hdev->asic_specific; in goya_hw_queues_unlock()
5223 spin_unlock(&goya->hw_queues_lock); in goya_hw_queues_unlock()
5228 return hdev->pdev->device; in goya_get_pci_id()
5234 struct goya_device *goya = hdev->asic_specific; in goya_get_eeprom_data()
5236 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_get_eeprom_data()
5249 if (ctx->asid != HL_KERNEL_ASID_ID) in goya_ctx_init()
5250 goya_mmu_prepare(ctx->hdev, ctx->asid); in goya_ctx_init()
5313 return -EINVAL; in goya_collective_wait_create_jobs()
5324 return -EPERM; in goya_get_hw_block_id()
5330 return -EPERM; in goya_block_mmap()
5341 return -EINVAL; in goya_ack_mmu_page_fault_or_access_error()
5354 default: return -EINVAL; in goya_map_pll_idx_to_fw_idx()
5400 hdev->state_dump_specs.props = goya_state_dump_specs_props; in goya_state_dump_init()
5401 hdev->state_dump_specs.funcs = goya_state_dump_funcs; in goya_state_dump_init()
5416 return -EOPNOTSUPP; in goya_get_monitor_dump()
5425 return -EOPNOTSUPP; in goya_scrub_device_dram()
5541 * goya_set_asic_funcs - set Goya function pointers
5548 hdev->asic_funcs = &goya_funcs; in goya_set_asic_funcs()