Lines Matching +full:0 +full:x1f
15 ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
16 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
17 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
20 ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
21 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
22 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
23 (0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT))
26 (0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT)
29 ((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \
30 (0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT))
37 ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
38 (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
39 (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))
42 ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
43 (0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \
44 (0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \
45 (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
46 (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))
49 ((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
50 (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
51 (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \
52 (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
55 ((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
56 (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
57 (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \
58 (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
61 ((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
62 (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
63 (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \
64 (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
87 #define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
89 #define DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40
104 #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
105 #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
106 #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
113 #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
114 #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2
116 #define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK GENMASK(1, 0)
123 #define SM_CQ_L2H_MASK_VAL 0xFFFFFFFFFC000000ull
124 #define SM_CQ_L2H_CMPR_VAL 0x1000007FFC000000ull
133 #define AXUSER_HB_SEC_ASID_MASK 0x3FF
134 #define AXUSER_HB_SEC_MMBP_MASK 0x400
138 #define ROT_MSS_HALT_WBC_MASK BIT(0)
142 #define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT 0
143 #define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK 0x1
146 #define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK 0x8000
148 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_SHIFT 0
149 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK 0x1
151 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK 0x2
153 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK 0x4
155 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_MASK 0x8
157 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_MASK 0x10
159 #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_MASK 0x20