156 static inline bool validate_packet_id(enum packet_id id)  in validate_packet_id()  argument
158 	switch (id) {  in validate_packet_id()
347 	{ .id = 0,  .name = "SYNC_OBJ_DMA_DOWN_FEEDBACK" },
348 	{ .id = 1,  .name = "SYNC_OBJ_DMA_UP_FEEDBACK" },
349 	{ .id = 2,  .name = "SYNC_OBJ_DMA_STATIC_DRAM_SRAM_FEEDBACK" },
350 	{ .id = 3,  .name = "SYNC_OBJ_DMA_SRAM_DRAM_FEEDBACK" },
351 	{ .id = 4,  .name = "SYNC_OBJ_FIRST_COMPUTE_FINISH" },
352 	{ .id = 5,  .name = "SYNC_OBJ_HOST_DRAM_DONE" },
353 	{ .id = 6,  .name = "SYNC_OBJ_DBG_CTR_DEPRECATED" },
354 	{ .id = 7,  .name = "SYNC_OBJ_DMA_ACTIVATIONS_DRAM_SRAM_FEEDBACK" },
355 	{ .id = 8,  .name = "SYNC_OBJ_ENGINE_SEM_MME_0" },
356 	{ .id = 9,  .name = "SYNC_OBJ_ENGINE_SEM_MME_1" },
357 	{ .id = 10, .name = "SYNC_OBJ_ENGINE_SEM_TPC_0" },
358 	{ .id = 11, .name = "SYNC_OBJ_ENGINE_SEM_TPC_1" },
359 	{ .id = 12, .name = "SYNC_OBJ_ENGINE_SEM_TPC_2" },
360 	{ .id = 13, .name = "SYNC_OBJ_ENGINE_SEM_TPC_3" },
361 	{ .id = 14, .name = "SYNC_OBJ_ENGINE_SEM_TPC_4" },
362 	{ .id = 15, .name = "SYNC_OBJ_ENGINE_SEM_TPC_5" },
363 	{ .id = 16, .name = "SYNC_OBJ_ENGINE_SEM_TPC_6" },
364 	{ .id = 17, .name = "SYNC_OBJ_ENGINE_SEM_TPC_7" },
365 	{ .id = 18, .name = "SYNC_OBJ_ENGINE_SEM_DMA_1" },
366 	{ .id = 19, .name = "SYNC_OBJ_ENGINE_SEM_DMA_2" },
367 	{ .id = 20, .name = "SYNC_OBJ_ENGINE_SEM_DMA_3" },
368 	{ .id = 21, .name = "SYNC_OBJ_ENGINE_SEM_DMA_4" },
369 	{ .id = 22, .name = "SYNC_OBJ_ENGINE_SEM_DMA_5" },
370 	{ .id = 23, .name = "SYNC_OBJ_ENGINE_SEM_DMA_6" },
371 	{ .id = 24, .name = "SYNC_OBJ_ENGINE_SEM_DMA_7" },
372 	{ .id = 25, .name = "SYNC_OBJ_DBG_CTR_0" },
373 	{ .id = 26, .name = "SYNC_OBJ_DBG_CTR_1" },
377 	{ .id = 200, .name = "MON_OBJ_DMA_DOWN_FEEDBACK_RESET" },
378 	{ .id = 201, .name = "MON_OBJ_DMA_UP_FEEDBACK_RESET" },
379 	{ .id = 203, .name = "MON_OBJ_DRAM_TO_SRAM_QUEUE_FENCE" },
380 	{ .id = 204, .name = "MON_OBJ_TPC_0_CLK_GATE" },
381 	{ .id = 205, .name = "MON_OBJ_TPC_1_CLK_GATE" },
382 	{ .id = 206, .name = "MON_OBJ_TPC_2_CLK_GATE" },
383 	{ .id = 207, .name = "MON_OBJ_TPC_3_CLK_GATE" },
384 	{ .id = 208, .name = "MON_OBJ_TPC_4_CLK_GATE" },
385 	{ .id = 209, .name = "MON_OBJ_TPC_5_CLK_GATE" },
386 	{ .id = 210, .name = "MON_OBJ_TPC_6_CLK_GATE" },
387 	{ .id = 211, .name = "MON_OBJ_TPC_7_CLK_GATE" },
1005 	job->id = 0;  in _gaudi_init_tpc_mem()
1480 	job->id = 0;  in gaudi_collective_wait_create_job()
1809 	struct pci_mem_region *region;  in gaudi_set_pci_memory_regions()  local
1812 	region = &hdev->pci_mem_region[PCI_REGION_CFG];  in gaudi_set_pci_memory_regions()
1813 	region->region_base = CFG_BASE;  in gaudi_set_pci_memory_regions()
1814 	region->region_size = CFG_SIZE;  in gaudi_set_pci_memory_regions()
1815 	region->offset_in_bar = CFG_BASE - SPI_FLASH_BASE_ADDR;  in gaudi_set_pci_memory_regions()
1816 	region->bar_size = CFG_BAR_SIZE;  in gaudi_set_pci_memory_regions()
1817 	region->bar_id = CFG_BAR_ID;  in gaudi_set_pci_memory_regions()
1818 	region->used = 1;  in gaudi_set_pci_memory_regions()
1821 	region = &hdev->pci_mem_region[PCI_REGION_SRAM];  in gaudi_set_pci_memory_regions()
1822 	region->region_base = SRAM_BASE_ADDR;  in gaudi_set_pci_memory_regions()
1823 	region->region_size = SRAM_SIZE;  in gaudi_set_pci_memory_regions()
1824 	region->offset_in_bar = 0;  in gaudi_set_pci_memory_regions()
1825 	region->bar_size = SRAM_BAR_SIZE;  in gaudi_set_pci_memory_regions()
1826 	region->bar_id = SRAM_BAR_ID;  in gaudi_set_pci_memory_regions()
1827 	region->used = 1;  in gaudi_set_pci_memory_regions()
1830 	region = &hdev->pci_mem_region[PCI_REGION_DRAM];  in gaudi_set_pci_memory_regions()
1831 	region->region_base = DRAM_PHYS_BASE;  in gaudi_set_pci_memory_regions()
1832 	region->region_size = hdev->asic_prop.dram_size;  in gaudi_set_pci_memory_regions()
1833 	region->offset_in_bar = 0;  in gaudi_set_pci_memory_regions()
1834 	region->bar_size = prop->dram_pci_bar_size;  in gaudi_set_pci_memory_regions()
1835 	region->bar_id = HBM_BAR_ID;  in gaudi_set_pci_memory_regions()
1836 	region->used = 1;  in gaudi_set_pci_memory_regions()
1839 	region = &hdev->pci_mem_region[PCI_REGION_SP_SRAM];  in gaudi_set_pci_memory_regions()
1840 	region->region_base = PSOC_SCRATCHPAD_ADDR;  in gaudi_set_pci_memory_regions()
1841 	region->region_size = PSOC_SCRATCHPAD_SIZE;  in gaudi_set_pci_memory_regions()
1842 	region->offset_in_bar = PSOC_SCRATCHPAD_ADDR - SPI_FLASH_BASE_ADDR;  in gaudi_set_pci_memory_regions()
1843 	region->bar_size = CFG_BAR_SIZE;  in gaudi_set_pci_memory_regions()
1844 	region->bar_id = CFG_BAR_ID;  in gaudi_set_pci_memory_regions()
1845 	region->used = 1;  in gaudi_set_pci_memory_regions()
5612 	job->id = 0;  in gaudi_memset_device_memory()
5688 	job->id = 0;  in gaudi_memset_registers()
7325 			eq_nic_sei->id);  in gaudi_print_nic_axi_irq_info()
8950 		mon->id, name,  in gaudi_print_single_monitor()
9056 			gaudi_so_id_to_str[i].id);  in gaudi_state_dump_init()
9061 			gaudi_monitor_id_to_str[i].id);  in gaudi_state_dump_init()
9110 	dev_vrm_attr_grp->attrs = gaudi_vrm_dev_attrs;  in gaudi_add_device_attr()