Lines Matching +full:0 +full:x184
20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0x..x 8-bit IPI partition register
30 * 0200 0...0m..m RunStall core 'n'
34 #define MIROUT(irq) (0x000 + (irq))
35 #define MIPICAUSE(cpu) (0x100 + (cpu))
36 #define MIPISET(cause) (0x140 + (cause))
37 #define MIENG 0x180
38 #define MIENGSET 0x184
39 #define MIASG 0x188 /* Read Global Assert Register */
40 #define MIASGSET 0x18c /* Set Global Addert Regiter */
41 #define MIPIPART 0x190
42 #define SYSCFGID 0x1a0
43 #define MPSCORE 0x200
44 #define CCON 0x220