45 #define KB (1024)  macro
46 #define SIZE_TO_MASK(size) (~(size - 1))
57 	pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,  in reg_init()
74 	pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,  in sata_reg_init()
106 	DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
107 	DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
108 	DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
109 	DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
110 	DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
111 	DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
112 	DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
113 	DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
114 	DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
115 	DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
116 	DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
117 	DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
122 	DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
129 	DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
131 	DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
133 	DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
135 	DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
136 	DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
137 	DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
145 	DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
146 	DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
147 	DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
151 	DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
152 	DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
183 	case PCI_BASE_ADDRESS_0 + 1:  in bridge_read()
198 		*value = 1;  in bridge_read()
207 		av_bridge_limit = av_bridge_base + (512*MB - 1);  in bridge_read()
238 		retval = 1;  in bridge_read()
260 	return -1;  in ce4100_bus1_read()
268 	if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value))  in ce4100_conf_read()
271 	if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&  in ce4100_conf_read()
294 	return -1;  in ce4100_bus1_write()
302 	if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value))  in ce4100_conf_write()
306 	if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&  in ce4100_conf_write()
323 	return 1;  in ce4100_pci_init()