Lines Matching +full:ecx +full:- +full:2000
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
25 #include <asm/intel-family.h>
61 return hdr->datasize ? hdr->totalsize : DEFAULT_UCODE_TOTALSIZE; in get_totalsize()
66 return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; in exttable_size()
74 unsigned int eax, ebx, ecx, edx; in intel_cpu_collect_info() local
79 ecx = 0; in intel_cpu_collect_info()
80 native_cpuid(&eax, &ebx, &ecx, &edx); in intel_cpu_collect_info()
94 uci->cpu_sig = csig; in intel_cpu_collect_info()
110 if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) in intel_find_matching_signature()
120 for (i = 0; i < ext_hdr->count; i++) { in intel_find_matching_signature()
121 if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) in intel_find_matching_signature()
130 * intel_microcode_sanity_check() - Sanity check microcode file.
140 * Return: 0 if the file passes all the checks, -EINVAL if any of the checks
157 return -EINVAL; in intel_microcode_sanity_check()
160 if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { in intel_microcode_sanity_check()
163 mc_header->hdrver); in intel_microcode_sanity_check()
164 return -EINVAL; in intel_microcode_sanity_check()
167 ext_table_size = total_size - (MC_HEADER_SIZE + data_size); in intel_microcode_sanity_check()
173 ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { in intel_microcode_sanity_check()
176 return -EINVAL; in intel_microcode_sanity_check()
183 return -EFAULT; in intel_microcode_sanity_check()
186 ext_sigcount = ext_header->count; in intel_microcode_sanity_check()
195 while (i--) in intel_microcode_sanity_check()
201 return -EINVAL; in intel_microcode_sanity_check()
212 while (i--) in intel_microcode_sanity_check()
218 return -EINVAL; in intel_microcode_sanity_check()
231 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - in intel_microcode_sanity_check()
232 (ext_sig->sig + ext_sig->pf + ext_sig->cksum); in intel_microcode_sanity_check()
236 return -EINVAL; in intel_microcode_sanity_check()
250 if (mc_hdr->rev <= new_rev) in has_newer_microcode()
264 p->data = kmemdup(data, size, GFP_KERNEL); in memdup_patch()
265 if (!p->data) { in memdup_patch()
283 mc_saved_hdr = (struct microcode_header_intel *)iter->data; in save_microcode_patch()
284 sig = mc_saved_hdr->sig; in save_microcode_patch()
285 pf = mc_saved_hdr->pf; in save_microcode_patch()
290 if (mc_hdr->rev <= mc_saved_hdr->rev) in save_microcode_patch()
297 list_replace(&iter->plist, &p->plist); in save_microcode_patch()
298 kfree(iter->data); in save_microcode_patch()
313 list_add_tail(&p->plist, µcode_cache); in save_microcode_patch()
319 if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) in save_microcode_patch()
323 * Save for early loading. On 32-bit, that needs to be a physical in save_microcode_patch()
328 intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data); in save_microcode_patch()
330 intel_ucode_patch = p->data; in save_microcode_patch()
356 size -= mc_size; in scan_microcode()
358 if (!intel_find_matching_signature(data, uci->cpu_sig.sig, in scan_microcode()
359 uci->cpu_sig.pf)) { in scan_microcode()
372 uci->cpu_sig.sig, in scan_microcode()
373 uci->cpu_sig.pf, in scan_microcode()
374 uci->cpu_sig.rev)) in scan_microcode()
378 struct microcode_header_intel *phdr = &patch->hdr; in scan_microcode()
381 phdr->sig, in scan_microcode()
382 phdr->pf, in scan_microcode()
383 phdr->rev)) in scan_microcode()
402 unsigned int eax = 1, ebx, ecx = 0, edx; in load_builtin_intel_microcode() local
409 native_cpuid(&eax, &ebx, &ecx, &edx); in load_builtin_intel_microcode()
411 sprintf(name, "intel-ucode/%02x-%02x-%02x", in load_builtin_intel_microcode()
415 cp->size = fw.size; in load_builtin_intel_microcode()
416 cp->data = (void *)fw.data; in load_builtin_intel_microcode()
425 pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", in print_ucode_info()
484 mc = uci->mc; in apply_microcode_early()
489 * Save us the MSR write below - which is a particular expensive in apply_microcode_early()
490 * operation - when the other hyperthread has updated the microcode in apply_microcode_early()
494 if (rev >= mc->hdr.rev) { in apply_microcode_early()
495 uci->cpu_sig.rev = rev; in apply_microcode_early()
508 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in apply_microcode_early()
511 if (rev != mc->hdr.rev) in apply_microcode_early()
512 return -1; in apply_microcode_early()
514 uci->cpu_sig.rev = rev; in apply_microcode_early()
517 print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); in apply_microcode_early()
519 print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); in apply_microcode_early()
566 /* try built-in microcode first */ in __load_ucode_intel()
622 phdr = (struct microcode_header_intel *)iter->data; in find_patch()
624 if (phdr->rev <= uci->cpu_sig.rev) in find_patch()
628 uci->cpu_sig.sig, in find_patch()
629 uci->cpu_sig.pf)) in find_patch()
632 return iter->data; in find_patch()
660 csig->sig = cpuid_eax(0x00000001); in collect_cpu_info()
662 if ((c->x86_model >= 5) || (c->x86 > 6)) { in collect_cpu_info()
665 csig->pf = 1 << ((val[1] >> 18) & 7); in collect_cpu_info()
668 csig->rev = c->microcode; in collect_cpu_info()
677 bool bsp = c->cpu_index == boot_cpu_data.cpu_index; in apply_microcode_intel()
690 mc = uci->mc; in apply_microcode_intel()
696 * Save us the MSR write below - which is a particular expensive in apply_microcode_intel()
697 * operation - when the other hyperthread has updated the microcode in apply_microcode_intel()
701 if (rev >= mc->hdr.rev) { in apply_microcode_intel()
713 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in apply_microcode_intel()
717 if (rev != mc->hdr.rev) { in apply_microcode_intel()
719 cpu, mc->hdr.rev); in apply_microcode_intel()
724 pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", in apply_microcode_intel()
726 mc->hdr.date & 0xffff, in apply_microcode_intel()
727 mc->hdr.date >> 24, in apply_microcode_intel()
728 (mc->hdr.date >> 16) & 0xff); in apply_microcode_intel()
735 uci->cpu_sig.rev = rev; in apply_microcode_intel()
736 c->microcode = rev; in apply_microcode_intel()
750 int new_rev = uci->cpu_sig.rev; in generic_load_microcode()
769 data_size = mc_size - sizeof(mc_header); in generic_load_microcode()
791 csig = uci->cpu_sig.sig; in generic_load_microcode()
792 cpf = uci->cpu_sig.pf; in generic_load_microcode()
813 vfree(uci->mc); in generic_load_microcode()
814 uci->mc = (struct microcode_intel *)new_mc; in generic_load_microcode()
820 cpu, new_rev, uci->cpu_sig.rev); in generic_load_microcode()
833 * Processor E7-8800/4800 v4 Product Family). in is_blacklisted()
835 if (c->x86 == 6 && in is_blacklisted()
836 c->x86_model == INTEL_FAM6_BROADWELL_X && in is_blacklisted()
837 c->x86_stepping == 0x01 && in is_blacklisted()
839 c->microcode < 0x0b000021) { in is_blacklisted()
840 …pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microc… in is_blacklisted()
841 …pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS upda… in is_blacklisted()
860 sprintf(name, "intel-ucode/%02x-%02x-%02x", in request_microcode_fw()
861 c->x86, c->x86_model, c->x86_stepping); in request_microcode_fw()
868 kvec.iov_base = (void *)firmware->data; in request_microcode_fw()
869 kvec.iov_len = firmware->size; in request_microcode_fw()
870 iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size); in request_microcode_fw()
886 u64 llc_size = c->x86_cache_size * 1024ULL; in calc_llc_size_per_core()
888 do_div(llc_size, c->x86_max_cores); in calc_llc_size_per_core()
897 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || in init_intel_microcode()
899 pr_err("Intel CPU family 0x%x not supported\n", c->x86); in init_intel_microcode()