1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
60  * With a name like MSR_TEST_CTL it should go without saying, but don't touch
67  * Processors which have self-snooping capability can handle conflicting
75 	switch (c->x86_model) {  in check_memory_type_self_snoop_errata()
107 	if (c->x86 != 6)  in probe_xeon_phi_r3mwait()
109 	switch (c->x86_model) {  in probe_xeon_phi_r3mwait()
131  * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132  * - https://kb.vmware.com/s/article/52345
133  * - Microcode revisions observed in the wild
134  * - Release note from 20180108 microcode release
176 	if (c->x86 != 6)  in bad_spectre_microcode()
180 		if (c->x86_model == spectre_bad_microcodes[i].model &&  in bad_spectre_microcode()
181 		    c->x86_stepping == spectre_bad_microcodes[i].stepping)  in bad_spectre_microcode()
182 			return (c->microcode <= spectre_bad_microcodes[i].microcode);  in bad_spectre_microcode()
192 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
195 			c->cpuid_level = cpuid_eax(0);  in early_init_intel()
200 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||  in early_init_intel()
201 		(c->x86 == 0x6 && c->x86_model >= 0x0e))  in early_init_intel()
204 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))  in early_init_intel()
205 		c->microcode = intel_get_microcode_revision();  in early_init_intel()
231 	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&  in early_init_intel()
232 	    c->microcode < 0x20e) {  in early_init_intel()
241 	if (c->x86 == 15 && c->x86_cache_alignment == 64)  in early_init_intel()
242 		c->x86_cache_alignment = 128;  in early_init_intel()
246 	if (c->x86 == 0xF && c->x86_model == 0x3  in early_init_intel()
247 	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))  in early_init_intel()
248 		c->x86_phys_bits = 36;  in early_init_intel()
251 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_intel()
252 	 * with P/T states and does not stop in deep C-states.  in early_init_intel()
255 	 * cabinets - we turn it off in that case explicitly.)  in early_init_intel()
257 	if (c->x86_power & (1 << 8)) {  in early_init_intel()
263 	if (c->x86 == 6) {  in early_init_intel()
264 		switch (c->x86_model) {  in early_init_intel()
286 	if (c->x86 == 6 && c->x86_model < 15)  in early_init_intel()
293 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
312 	if (c->x86 == 5 && c->x86_model == 9) {  in early_init_intel()
317 	if (c->cpuid_level >= 0x00000001) {  in early_init_intel()
327 			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);  in early_init_intel()
368 	if (!c->cpu_index)  in intel_smp_check()
374 	if (c->x86 == 5 &&  in intel_smp_check()
375 	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&  in intel_smp_check()
376 	    c->x86_model <= 3) {  in intel_smp_check()
403 	if (c->x86 == 5 && c->x86_model < 9) {  in intel_workarounds()
408 			pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");  in intel_workarounds()
418 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)  in intel_workarounds()
436 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {  in intel_workarounds()
450 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&  in intel_workarounds()
451 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))  in intel_workarounds()
459 	switch (c->x86) {  in intel_workarounds()
464 	case 6:		/* PII/PIII only like movsl with 8-byte alignment */  in intel_workarounds()
467 	case 15:	/* P4 is OK down to 8-byte alignment */  in intel_workarounds()
562 	nr_keyids = (1UL << keyid_bits) - 1;  in detect_tme()
579 	c->x86_phys_bits -= keyid_bits;  in detect_tme()
639 	if (c->cpuid_level > 9) {  in init_intel()
659 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&  in init_intel()
660 	    (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))  in init_intel()
663 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&  in init_intel()
664 		((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))  in init_intel()
668 	if (c->x86 == 15)  in init_intel()
669 		c->x86_cache_alignment = c->x86_clflush_size * 2;  in init_intel()
670 	if (c->x86 == 6)  in init_intel()
678 	if (c->x86 == 6) {  in init_intel()
679 		unsigned int l2 = c->x86_cache_size;  in init_intel()
682 		switch (c->x86_model) {  in init_intel()
693 			else if (c->x86_stepping == 0 || c->x86_stepping == 5)  in init_intel()
694 				p = "Celeron-A";  in init_intel()
704 			strcpy(c->x86_model_id, p);  in init_intel()
707 	if (c->x86 == 15)  in init_intel()
709 	if (c->x86 == 6)  in init_intel()
738 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))  in intel_size_cache()
742 	 * Intel Quark SoC X1000 contains a 4-way set associative  in intel_size_cache()
745 	if ((c->x86 == 5) && (c->x86_model == 9))  in intel_size_cache()
773 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
775 	{ 0x03, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way set associative" },
776 	{ 0x04, TLB_DATA_4M,		8,	" TLB_DATA 4 MByte pages, 4-way set associative" },
777 	{ 0x05, TLB_DATA_4M,		32,	" TLB_DATA 4 MByte pages, 4-way set associative" },
778 	{ 0x0b, TLB_INST_4M,		4,	" TLB_INST 4 MByte pages, 4-way set associative" },
780 	{ 0x50, TLB_INST_ALL,		64,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
781 	{ 0x51, TLB_INST_ALL,		128,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
782 	{ 0x52, TLB_INST_ALL,		256,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
783 	{ 0x55, TLB_INST_2M_4M,		7,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
784 	{ 0x56, TLB_DATA0_4M,		16,	" TLB_DATA0 4 MByte pages, 4-way set associative" },
785 	{ 0x57, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, 4-way associative" },
787 	{ 0x5a, TLB_DATA0_2M_4M,	32,	" TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
792 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
793 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
794 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
796 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
797 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
798 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
799 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
800 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
801 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
802 	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },
803 	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },
804 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
805 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
806 	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
807 	{ 0xc2, TLB_DATA_2M_4M,		16,	" TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
808 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
905 	if (c->cpuid_level < 2)  in intel_detect_tlb()
932 			  [0] = "486 DX-25/33",
933 			  [1] = "486 DX-50",
938 			  [7] = "486 DX/2-WB",
940 			  [9] = "486 DX/4-WB"
945 			  [0] = "Pentium 60/66 A-step",
947 			  [2] = "Pentium 75 - 200",
950 			  [7] = "Mobile Pentium 75 - 200",
957 			  [0] = "Pentium Pro A-step",
1156  * If a CPU goes offline with pending delayed work to re-enable split lock
1159  * different CPU probably won't re-enable split lock detection. This is a
1163  * Unconditionally re-enable detection here.
1177 	if (!current->reported_split_lock)  in split_lock_warn()
1179 				    current->comm, current->pid, ip);  in split_lock_warn()
1180 	current->reported_split_lock = 1;  in split_lock_warn()
1193 		if (down_interruptible(&buslock_sem) == -EINTR)  in split_lock_warn()
1216 		     current->comm, current->pid,  in handle_guest_split_lock()
1219 	current->thread.error_code = 0;  in handle_guest_split_lock()
1220 	current->thread.trap_nr = X86_TRAP_AC;  in handle_guest_split_lock()
1252 	if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)  in handle_user_split_lock()
1254 	split_lock_warn(regs->ip);  in handle_user_split_lock()
1271 				    current->comm, current->pid, regs->ip);  in handle_bus_lock()
1280  * CPU models that are known to have the per-core split-lock detection
1335 …	pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");  in sld_state_show()
1340 			pr_info("#DB: warning on user-space bus_locks\n");  in sld_state_show()
1345 …pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_loc…  in sld_state_show()
1347 			pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",  in sld_state_show()
1349 				" from non-WB" : "");  in sld_state_show()
1369  * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU