Lines Matching +full:4 +full:k
375 c->x86_stepping >= 1 && c->x86_stepping <= 4 && in intel_smp_check()
418 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
450 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
460 case 4: /* 486: untested */ in intel_workarounds()
504 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
742 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
743 * 16K cache with a 16 byte cache line and 256 lines per tag in intel_size_cache()
773 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
774 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
775 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
776 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
777 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
778 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
779 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
780 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
781 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
782 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
783 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
784 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
785 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
786 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
787 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
788 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
789 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
790 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
791 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
792 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
793 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
794 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
796 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
797 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
798 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
799 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
800 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
801 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
802 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
803 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
804 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
805 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
806 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
807 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
808 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
814 unsigned char k; in intel_tlb_lookup() local
819 for (k = 0; intel_tlb_table[k].descriptor != desc && in intel_tlb_lookup()
820 intel_tlb_table[k].descriptor != 0; k++) in intel_tlb_lookup()
823 if (intel_tlb_table[k].tlb_type == 0) in intel_tlb_lookup()
826 switch (intel_tlb_table[k].tlb_type) { in intel_tlb_lookup()
828 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
829 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
830 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
831 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
834 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
835 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
836 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
837 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
838 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
839 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
840 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
841 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
842 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
843 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
844 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
845 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
848 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
849 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
850 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
851 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
852 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
853 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
856 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
857 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
860 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
861 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
864 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
865 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
866 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
867 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
871 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
872 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
876 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
877 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
881 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
882 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
883 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
884 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
887 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
888 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
889 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
890 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
893 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
894 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
902 unsigned int regs[4]; in intel_detect_tlb()
930 { .family = 4, .model_names =
936 [4] = "486 SL",
939 [8] = "486 DX/4",
940 [9] = "486 DX/4-WB"
949 [4] = "Pentium MMX",
960 [4] = "Pentium II (Deschutes)",
971 [0] = "Pentium 4 (Unknown)",
972 [1] = "Pentium 4 (Willamette)",
973 [2] = "Pentium 4 (Northwood)",
974 [4] = "Pentium 4 (Foster)",
975 [5] = "Pentium 4 (Foster)",