Lines Matching +full:ecx +full:- +full:2000
1 // SPDX-License-Identifier: GPL-2.0-only
62 #include <asm/intel-family.h>
140 info = (struct ppin_info *)id->driver_data; in ppin_init()
142 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) in ppin_init()
152 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); in ppin_init()
153 rdmsrl_safe(info->msr_ppin_ctl, &val); in ppin_init()
158 c->ppin = __rdmsr(info->msr_ppin); in ppin_init()
159 set_cpu_cap(c, info->feature); in ppin_init()
164 clear_cpu_cap(c, info->feature); in ppin_init()
174 if (c->cpuid_level == -1) { in default_init()
176 if (c->x86 == 4) in default_init()
177 strcpy(c->x86_model_id, "486"); in default_init()
178 else if (c->x86 == 3) in default_init()
179 strcpy(c->x86_model_id, "386"); in default_init()
196 * IRET will check the segment types kkeil 2000/10/28
218 /* 32-bit code */
220 /* 16-bit code */
222 /* 16-bit data */
224 /* 16-bit data */
226 /* 16-bit data */
232 /* 32-bit code */
234 /* 16-bit code */
250 return -EINVAL; in x86_nopcid_setup()
267 return -EINVAL; in x86_noinvpcid_setup()
280 static int cachesize_override = -1;
342 c->cpuid_level = cpuid_eax(0); in squash_the_stupid_serial_number()
514 * Protection Keys are not available in 32-bit mode.
632 * software. Add those features to this table to auto-disable them.
651 for (df = cpuid_dependent_features; df->feature; df++) { in filter_cpuid_features()
653 if (!cpu_has(c, df->feature)) in filter_cpuid_features()
656 * Note: cpuid_level is set to -1 if unavailable, but in filter_cpuid_features()
662 if (!((s32)df->level < 0 ? in filter_cpuid_features()
663 (u32)df->level > (u32)c->extended_cpuid_level : in filter_cpuid_features()
664 (s32)df->level > (s32)c->cpuid_level)) in filter_cpuid_features()
667 clear_cpu_cap(c, df->feature); in filter_cpuid_features()
672 x86_cap_flag(df->feature), df->level); in filter_cpuid_features()
689 if (c->x86_model >= 16) in table_lookup_model()
695 info = this_cpu->legacy_models; in table_lookup_model()
697 while (info->family) { in table_lookup_model()
698 if (info->family == c->x86) in table_lookup_model()
699 return info->model_names[c->x86_model]; in table_lookup_model()
711 /* The 32-bit entry code needs to find cpu_entry_area. */
715 /* Load the original GDT from the per-cpu structure */
721 gdt_descr.size = GDT_SIZE - 1; in load_direct_gdt()
726 /* Load a fixmap remapping of the per-cpu GDT */
732 gdt_descr.size = GDT_SIZE - 1; in load_fixmap_gdt()
738 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
742 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
785 if (c->extended_cpuid_level < 0x80000004) in get_model_name()
788 v = (unsigned int *)c->x86_model_id; in get_model_name()
792 c->x86_model_id[48] = 0; in get_model_name()
795 p = q = s = &c->x86_model_id[0]; in get_model_name()
801 /* Note the last non-whitespace index */ in get_model_name()
813 unsigned int eax, ebx, ecx, edx; in detect_num_cpu_cores() local
815 c->x86_max_cores = 1; in detect_num_cpu_cores()
816 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) in detect_num_cpu_cores()
819 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); in detect_num_cpu_cores()
821 c->x86_max_cores = (eax >> 26) + 1; in detect_num_cpu_cores()
826 unsigned int n, dummy, ebx, ecx, edx, l2size; in cpu_detect_cache_sizes() local
828 n = c->extended_cpuid_level; in cpu_detect_cache_sizes()
831 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); in cpu_detect_cache_sizes()
832 c->x86_cache_size = (ecx>>24) + (edx>>24); in cpu_detect_cache_sizes()
835 c->x86_tlbsize = 0; in cpu_detect_cache_sizes()
842 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); in cpu_detect_cache_sizes()
843 l2size = ecx >> 16; in cpu_detect_cache_sizes()
846 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); in cpu_detect_cache_sizes()
848 /* do processor-specific cache resizing */ in cpu_detect_cache_sizes()
849 if (this_cpu->legacy_cache_size) in cpu_detect_cache_sizes()
850 l2size = this_cpu->legacy_cache_size(c, l2size); in cpu_detect_cache_sizes()
853 if (cachesize_override != -1) in cpu_detect_cache_sizes()
860 c->x86_cache_size = l2size; in cpu_detect_cache_sizes()
873 if (this_cpu->c_detect_tlb) in cpu_detect_tlb()
874 this_cpu->c_detect_tlb(c); in cpu_detect_tlb()
888 u32 eax, ebx, ecx, edx; in detect_ht_early() local
891 return -1; in detect_ht_early()
894 return -1; in detect_ht_early()
897 return -1; in detect_ht_early()
899 cpuid(1, &eax, &ebx, &ecx, &edx); in detect_ht_early()
903 pr_info_once("CPU0: Hyper-Threading is disabled\n"); in detect_ht_early()
917 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); in detect_ht()
919 smp_num_siblings = smp_num_siblings / c->x86_max_cores; in detect_ht()
923 core_bits = get_count_order(c->x86_max_cores); in detect_ht()
925 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & in detect_ht()
926 ((1 << core_bits) - 1); in detect_ht()
932 char *v = c->x86_vendor_id; in get_cpu_vendor()
939 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || in get_cpu_vendor()
940 (cpu_devs[i]->c_ident[1] && in get_cpu_vendor()
941 !strcmp(v, cpu_devs[i]->c_ident[1]))) { in get_cpu_vendor()
944 c->x86_vendor = this_cpu->c_x86_vendor; in get_cpu_vendor()
952 c->x86_vendor = X86_VENDOR_UNKNOWN; in get_cpu_vendor()
959 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, in cpu_detect()
960 (unsigned int *)&c->x86_vendor_id[0], in cpu_detect()
961 (unsigned int *)&c->x86_vendor_id[8], in cpu_detect()
962 (unsigned int *)&c->x86_vendor_id[4]); in cpu_detect()
964 c->x86 = 4; in cpu_detect()
965 /* Intel-defined flags: level 0x00000001 */ in cpu_detect()
966 if (c->cpuid_level >= 0x00000001) { in cpu_detect()
970 c->x86 = x86_family(tfms); in cpu_detect()
971 c->x86_model = x86_model(tfms); in cpu_detect()
972 c->x86_stepping = x86_stepping(tfms); in cpu_detect()
975 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; in cpu_detect()
976 c->x86_cache_alignment = c->x86_clflush_size; in cpu_detect()
986 c->x86_capability[i] &= ~cpu_caps_cleared[i]; in apply_forced_caps()
987 c->x86_capability[i] |= cpu_caps_set[i]; in apply_forced_caps()
997 * Intel CPUs, for finer-grained selection of what's available. in init_speculation_control()
1034 u32 eax, ebx, ecx, edx; in get_cpu_cap() local
1036 /* Intel-defined flags: level 0x00000001 */ in get_cpu_cap()
1037 if (c->cpuid_level >= 0x00000001) { in get_cpu_cap()
1038 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1040 c->x86_capability[CPUID_1_ECX] = ecx; in get_cpu_cap()
1041 c->x86_capability[CPUID_1_EDX] = edx; in get_cpu_cap()
1045 if (c->cpuid_level >= 0x00000006) in get_cpu_cap()
1046 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); in get_cpu_cap()
1048 /* Additional Intel-defined flags: level 0x00000007 */ in get_cpu_cap()
1049 if (c->cpuid_level >= 0x00000007) { in get_cpu_cap()
1050 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1051 c->x86_capability[CPUID_7_0_EBX] = ebx; in get_cpu_cap()
1052 c->x86_capability[CPUID_7_ECX] = ecx; in get_cpu_cap()
1053 c->x86_capability[CPUID_7_EDX] = edx; in get_cpu_cap()
1055 /* Check valid sub-leaf index before accessing it */ in get_cpu_cap()
1057 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1058 c->x86_capability[CPUID_7_1_EAX] = eax; in get_cpu_cap()
1063 if (c->cpuid_level >= 0x0000000d) { in get_cpu_cap()
1064 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1066 c->x86_capability[CPUID_D_1_EAX] = eax; in get_cpu_cap()
1069 /* AMD-defined flags: level 0x80000001 */ in get_cpu_cap()
1071 c->extended_cpuid_level = eax; in get_cpu_cap()
1075 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1077 c->x86_capability[CPUID_8000_0001_ECX] = ecx; in get_cpu_cap()
1078 c->x86_capability[CPUID_8000_0001_EDX] = edx; in get_cpu_cap()
1082 if (c->extended_cpuid_level >= 0x80000007) { in get_cpu_cap()
1083 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1085 c->x86_capability[CPUID_8000_0007_EBX] = ebx; in get_cpu_cap()
1086 c->x86_power = edx; in get_cpu_cap()
1089 if (c->extended_cpuid_level >= 0x80000008) { in get_cpu_cap()
1090 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); in get_cpu_cap()
1091 c->x86_capability[CPUID_8000_0008_EBX] = ebx; in get_cpu_cap()
1094 if (c->extended_cpuid_level >= 0x8000000a) in get_cpu_cap()
1095 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); in get_cpu_cap()
1097 if (c->extended_cpuid_level >= 0x8000001f) in get_cpu_cap()
1098 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); in get_cpu_cap()
1100 if (c->extended_cpuid_level >= 0x80000021) in get_cpu_cap()
1101 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); in get_cpu_cap()
1108 * This needs to happen each time we re-probe, which may happen in get_cpu_cap()
1116 u32 eax, ebx, ecx, edx; in get_cpu_address_sizes() local
1118 if (c->extended_cpuid_level >= 0x80000008) { in get_cpu_address_sizes()
1119 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); in get_cpu_address_sizes()
1121 c->x86_virt_bits = (eax >> 8) & 0xff; in get_cpu_address_sizes()
1122 c->x86_phys_bits = eax & 0xff; in get_cpu_address_sizes()
1126 c->x86_phys_bits = 36; in get_cpu_address_sizes()
1128 c->x86_cache_bits = c->x86_phys_bits; in get_cpu_address_sizes()
1141 c->x86 = 4; in identify_cpu_without_cpuid()
1143 c->x86 = 3; in identify_cpu_without_cpuid()
1146 if (cpu_devs[i] && cpu_devs[i]->c_identify) { in identify_cpu_without_cpuid()
1147 c->x86_vendor_id[0] = 0; in identify_cpu_without_cpuid()
1148 cpu_devs[i]->c_identify(c); in identify_cpu_without_cpuid()
1149 if (c->x86_vendor_id[0]) { in identify_cpu_without_cpuid()
1220 * updated non-speculatively, and the issuing of %gs-relative memory
1229 /* AMD Family 0xf - 0x12 */
1235 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1266 /* CPU is affected by SMT (cross-thread) return predictions */
1315 return m && !!(m->driver_data & which); in cpu_matches()
1358 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature in cpu_set_bug_bits()
1359 * flag and protect from vendor-specific bugs via the whitelist. in cpu_set_bug_bits()
1380 * - TSX is supported or in cpu_set_bug_bits()
1381 * - TSX_CTRL is present in cpu_set_bug_bits()
1466 * probing for it doesn't even work. Disable it completely on 32-bit
1468 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1532 /* empty-string, i.e., ""-defined feature flags */ in cpu_parse_early_param()
1583 c->x86_clflush_size = 64; in early_identify_cpu()
1584 c->x86_phys_bits = 36; in early_identify_cpu()
1585 c->x86_virt_bits = 48; in early_identify_cpu()
1587 c->x86_clflush_size = 32; in early_identify_cpu()
1588 c->x86_phys_bits = 32; in early_identify_cpu()
1589 c->x86_virt_bits = 32; in early_identify_cpu()
1591 c->x86_cache_alignment = c->x86_clflush_size; in early_identify_cpu()
1593 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); in early_identify_cpu()
1594 c->extended_cpuid_level = 0; in early_identify_cpu()
1608 if (this_cpu->c_early_init) in early_identify_cpu()
1609 this_cpu->c_early_init(c); in early_identify_cpu()
1611 c->cpu_index = 0; in early_identify_cpu()
1614 if (this_cpu->c_bsp_init) in early_identify_cpu()
1615 this_cpu->c_bsp_init(c); in early_identify_cpu()
1629 * that it can't be enabled in 32-bit mode. in early_identify_cpu()
1636 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not in early_identify_cpu()
1638 * false-positives at the later stage. in early_identify_cpu()
1641 * - 5-level paging is disabled compile-time; in early_identify_cpu()
1642 * - it's 32-bit kernel; in early_identify_cpu()
1643 * - machine doesn't support 5-level paging; in early_identify_cpu()
1644 * - user specified 'no5lvl' in kernel command line. in early_identify_cpu()
1674 if (!cpudev->c_ident[j]) in early_cpu_init()
1676 pr_info(" %s %s\n", cpudev->c_vendor, in early_cpu_init()
1677 cpudev->c_ident[j]); in early_cpu_init()
1695 * detect it directly instead of hard-coding the choice by in detect_null_seg_behavior()
1736 if ((c->x86 == 0x17 || c->x86 == 0x18) && in check_null_seg_clears_base()
1746 c->extended_cpuid_level = 0; in generic_identify()
1763 if (c->cpuid_level >= 0x00000001) { in generic_identify()
1764 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; in generic_identify()
1767 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); in generic_identify()
1769 c->apicid = c->initial_apicid; in generic_identify()
1772 c->phys_proc_id = c->initial_apicid; in generic_identify()
1784 * NB: For the time being, only 32-bit kernels support in generic_identify()
1785 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose in generic_identify()
1787 * non-paravirt system ever shows up that does *not* have the in generic_identify()
1804 apicid = apic->cpu_present_to_apicid(cpu); in validate_apic_and_package_id()
1806 if (apicid != c->apicid) { in validate_apic_and_package_id()
1808 cpu, apicid, c->initial_apicid); in validate_apic_and_package_id()
1810 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); in validate_apic_and_package_id()
1811 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); in validate_apic_and_package_id()
1813 c->logical_proc_id = 0; in validate_apic_and_package_id()
1824 c->loops_per_jiffy = loops_per_jiffy; in identify_cpu()
1825 c->x86_cache_size = 0; in identify_cpu()
1826 c->x86_vendor = X86_VENDOR_UNKNOWN; in identify_cpu()
1827 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ in identify_cpu()
1828 c->x86_vendor_id[0] = '\0'; /* Unset */ in identify_cpu()
1829 c->x86_model_id[0] = '\0'; /* Unset */ in identify_cpu()
1830 c->x86_max_cores = 1; in identify_cpu()
1831 c->x86_coreid_bits = 0; in identify_cpu()
1832 c->cu_id = 0xff; in identify_cpu()
1834 c->x86_clflush_size = 64; in identify_cpu()
1835 c->x86_phys_bits = 36; in identify_cpu()
1836 c->x86_virt_bits = 48; in identify_cpu()
1838 c->cpuid_level = -1; /* CPUID not detected */ in identify_cpu()
1839 c->x86_clflush_size = 32; in identify_cpu()
1840 c->x86_phys_bits = 32; in identify_cpu()
1841 c->x86_virt_bits = 32; in identify_cpu()
1843 c->x86_cache_alignment = c->x86_clflush_size; in identify_cpu()
1844 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); in identify_cpu()
1846 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); in identify_cpu()
1851 if (this_cpu->c_identify) in identify_cpu()
1852 this_cpu->c_identify(c); in identify_cpu()
1858 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); in identify_cpu()
1862 * Vendor-specific initialization. In this section we in identify_cpu()
1868 * At the end of this section, c->x86_capability better in identify_cpu()
1871 if (this_cpu->c_init) in identify_cpu()
1872 this_cpu->c_init(c); in identify_cpu()
1889 * The vendor-specific functions might have changed features. in identify_cpu()
1897 if (!c->x86_model_id[0]) { in identify_cpu()
1901 strcpy(c->x86_model_id, p); in identify_cpu()
1904 sprintf(c->x86_model_id, "%02x/%02x", in identify_cpu()
1905 c->x86, c->x86_model); in identify_cpu()
1931 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; in identify_cpu()
1935 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; in identify_cpu()
1952 * on 32-bit kernels:
1967 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- in enable_sep_cpu()
1971 tss->x86_tss.ss1 = __KERNEL_CS; in enable_sep_cpu()
1972 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); in enable_sep_cpu()
2015 if (c->x86_vendor < X86_VENDOR_NUM) { in print_cpu_info()
2016 vendor = this_cpu->c_vendor; in print_cpu_info()
2018 if (c->cpuid_level >= 0) in print_cpu_info()
2019 vendor = c->x86_vendor_id; in print_cpu_info()
2022 if (vendor && !strstr(c->x86_model_id, vendor)) in print_cpu_info()
2025 if (c->x86_model_id[0]) in print_cpu_info()
2026 pr_cont("%s", c->x86_model_id); in print_cpu_info()
2028 pr_cont("%d86", c->x86); in print_cpu_info()
2030 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); in print_cpu_info()
2032 if (c->x86_stepping || c->cpuid_level >= 0) in print_cpu_info()
2033 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); in print_cpu_info()
2063 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR in wrmsrl_cstar()
2081 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. in syscall_init()
2083 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). in syscall_init()
2098 * to minimize user space-kernel interference. in syscall_init()
2163 d.d = 1; /* 32-bit */ in setup_getcpu()
2173 /* Set up the per-CPU TSS IST stacks */ in tss_setup_ist()
2174 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); in tss_setup_ist()
2175 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); in tss_setup_ist()
2176 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); in tss_setup_ist()
2177 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); in tss_setup_ist()
2178 /* Only mapped when SEV-ES is active */ in tss_setup_ist()
2179 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); in tss_setup_ist()
2195 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; in tss_setup_io_bitmap()
2198 tss->io_bitmap.prev_max = 0; in tss_setup_io_bitmap()
2199 tss->io_bitmap.prev_sequence = 0; in tss_setup_io_bitmap()
2200 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); in tss_setup_io_bitmap()
2205 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; in tss_setup_io_bitmap()
2224 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); in cpu_init_exception_handling()
2236 * cpu_init() initializes state that is per-CPU. Some data is already
2261 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); in cpu_init()
2272 cur->active_mm = &init_mm; in cpu_init()
2273 BUG_ON(cur->mm); in cpu_init()
2298 * store_cpu_caps() - Store a snapshot of CPU capabilities
2306 curr_info->cpuid_level = cpuid_eax(0); in store_cpu_caps()
2309 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, in store_cpu_caps()
2310 sizeof(curr_info->x86_capability)); in store_cpu_caps()
2317 * microcode_check() - Check if any CPU capabilities changed after an update.
2335 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, in microcode_check()
2336 sizeof(prev_info->x86_capability))) in microcode_check()
2340 …pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS… in microcode_check()
2382 init_utsname()->machine[1] = in arch_cpu_finalize_init()
2414 * not cause "plain-text" data to be decrypted when accessed. It in arch_cpu_finalize_init()
2415 * must be called after late_time_init() so that Hyper-V x86/x64 in arch_cpu_finalize_init()