Lines Matching +full:4 +full:- +full:byte
1 // SPDX-License-Identifier: GPL-2.0
6 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
33 #define LVL_3 4
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
68 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
69 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
70 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
71 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
72 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
73 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
74 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
75 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
76 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
77 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
78 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
79 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
80 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
81 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
82 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
83 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
84 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
85 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
86 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
87 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
88 { 0x48, LVL_2, MB(3) }, /* 12-way set assoc, 64 byte line size */
89 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
90 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
91 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
92 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
93 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
94 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
95 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
96 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
97 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
98 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
99 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
100 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
101 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
102 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
103 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
104 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
105 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
106 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
107 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
108 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
109 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
110 { 0x80, LVL_2, 512 }, /* 8-way set assoc, 64 byte line size */
111 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
112 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
113 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
114 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
115 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
116 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
117 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
118 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
119 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
120 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
121 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
122 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
123 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
124 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
125 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
126 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
127 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
128 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
129 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
130 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
131 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
149 unsigned int reserved:4;
202 unsigned lines_per_tag:4;
203 unsigned assoc:4;
212 unsigned lines_per_tag:4;
213 unsigned assoc:4;
223 [4] = 4,
231 [0xf] = 0xffff /* fully associative - no way to show this currently */
256 eax->full = 0; in amd_cpuid4()
257 ebx->full = 0; in amd_cpuid4()
258 ecx->full = 0; in amd_cpuid4()
268 if (!l1->val) in amd_cpuid4()
270 assoc = assocs[l1->assoc]; in amd_cpuid4()
271 line_size = l1->line_size; in amd_cpuid4()
272 lines_per_tag = l1->lines_per_tag; in amd_cpuid4()
273 size_in_kb = l1->size_in_kb; in amd_cpuid4()
300 eax->split.is_self_initializing = 1; in amd_cpuid4()
301 eax->split.type = types[leaf]; in amd_cpuid4()
302 eax->split.level = levels[leaf]; in amd_cpuid4()
303 eax->split.num_threads_sharing = 0; in amd_cpuid4()
304 eax->split.num_cores_on_die = __this_cpu_read(cpu_info.x86_max_cores) - 1; in amd_cpuid4()
308 eax->split.is_fully_associative = 1; in amd_cpuid4()
309 ebx->split.coherency_line_size = line_size - 1; in amd_cpuid4()
310 ebx->split.ways_of_associativity = assoc - 1; in amd_cpuid4()
311 ebx->split.physical_line_partition = lines_per_tag - 1; in amd_cpuid4()
312 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size / in amd_cpuid4()
313 (ebx->split.ways_of_associativity + 1) - 1; in amd_cpuid4()
323 struct amd_l3_cache *l3 = &nb->l3_cache; in amd_calc_l3_indices()
327 pci_read_config_dword(nb->misc, 0x1C4, &val); in amd_calc_l3_indices()
330 l3->subcaches[0] = sc0 = !(val & BIT(0)); in amd_calc_l3_indices()
331 l3->subcaches[1] = sc1 = !(val & BIT(4)); in amd_calc_l3_indices()
334 l3->subcaches[0] = sc0 += !(val & BIT(1)); in amd_calc_l3_indices()
335 l3->subcaches[1] = sc1 += !(val & BIT(5)); in amd_calc_l3_indices()
338 l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); in amd_calc_l3_indices()
339 l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13)); in amd_calc_l3_indices()
341 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1; in amd_calc_l3_indices()
355 pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®); in amd_get_l3_disable_slot()
361 return -1; in amd_get_l3_disable_slot()
368 struct amd_northbridge *nb = this_leaf->priv; in show_cache_disable()
396 * disable index in all 4 subcaches in amd_l3_disable_index()
398 for (i = 0; i < 4; i++) { in amd_l3_disable_index()
401 if (!nb->l3_cache.subcaches[i]) in amd_l3_disable_index()
404 pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); in amd_l3_disable_index()
414 pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); in amd_l3_disable_index()
419 * disable a L3 cache index by using a disable-slot
436 return -EEXIST; in amd_set_l3_disable_slot()
438 if (index > nb->l3_cache.indices) in amd_set_l3_disable_slot()
439 return -EINVAL; in amd_set_l3_disable_slot()
443 return -EEXIST; in amd_set_l3_disable_slot()
456 struct amd_northbridge *nb = this_leaf->priv; in store_cache_disable()
459 return -EPERM; in store_cache_disable()
461 cpu = cpumask_first(&this_leaf->shared_cpu_map); in store_cache_disable()
464 return -EINVAL; in store_cache_disable()
468 if (err == -EEXIST) in store_cache_disable()
492 int cpu = cpumask_first(&this_leaf->shared_cpu_map); in subcaches_show()
502 int cpu = cpumask_first(&this_leaf->shared_cpu_map); in subcaches_store()
506 return -EPERM; in subcaches_store()
509 return -EINVAL; in subcaches_store()
512 return -EINVAL; in subcaches_store()
527 umode_t mode = attr->mode; in cache_private_attrs_is_visible()
529 if (!this_leaf->priv) in cache_private_attrs_is_visible()
579 struct amd_northbridge *nb = this_leaf->priv; in cache_get_priv_group()
581 if (this_leaf->level < 3 || !nb) in cache_get_priv_group()
584 if (nb && nb->l3_cache.indices) in cache_get_priv_group()
599 this_leaf->nb = node_to_amd_nb(node); in amd_init_l3_cache()
600 if (this_leaf->nb && !this_leaf->nb->l3_cache.indices) in amd_init_l3_cache()
601 amd_calc_l3_indices(this_leaf->nb); in amd_init_l3_cache()
627 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); in cpuid4_cache_lookup_regs()
631 return -EIO; /* better error ? */ in cpuid4_cache_lookup_regs()
633 this_leaf->eax = eax; in cpuid4_cache_lookup_regs()
634 this_leaf->ebx = ebx; in cpuid4_cache_lookup_regs()
635 this_leaf->ecx = ecx; in cpuid4_cache_lookup_regs()
636 this_leaf->size = (ecx.split.number_of_sets + 1) * in cpuid4_cache_lookup_regs()
647 int i = -1; in find_num_cache_leaves()
649 if (c->x86_vendor == X86_VENDOR_AMD || in find_num_cache_leaves()
650 c->x86_vendor == X86_VENDOR_HYGON) in find_num_cache_leaves()
653 op = 4; in find_num_cache_leaves()
673 if (c->x86 < 0x17) { in cacheinfo_amd_init_llc_id()
675 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id; in cacheinfo_amd_init_llc_id()
676 } else if (c->x86 == 0x17 && c->x86_model <= 0x1F) { in cacheinfo_amd_init_llc_id()
681 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; in cacheinfo_amd_init_llc_id()
688 u32 llc_index = find_num_cache_leaves(c) - 1; in cacheinfo_amd_init_llc_id()
697 per_cpu(cpu_llc_id, cpu) = c->apicid >> bits; in cacheinfo_amd_init_llc_id()
715 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; in cacheinfo_hygon_init_llc_id()
723 } else if (c->extended_cpuid_level >= 0x80000006) { in init_amd_cacheinfo()
725 num_cache_leaves = 4; in init_amd_cacheinfo()
740 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ in init_intel_cacheinfo()
741 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ in init_intel_cacheinfo()
744 unsigned int cpu = c->cpu_index; in init_intel_cacheinfo()
747 if (c->cpuid_level > 3) { in init_intel_cacheinfo()
757 * Whenever possible use cpuid(4), deterministic cache in init_intel_cacheinfo()
779 l2_id = c->apicid & ~((1 << index_msb) - 1); in init_intel_cacheinfo()
785 l3_id = c->apicid & ~((1 << index_msb) - 1); in init_intel_cacheinfo()
796 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) { in init_intel_cacheinfo()
799 unsigned int regs[4]; in init_intel_cacheinfo()
803 if (num_cache_leaves != 0 && c->x86 == 15) in init_intel_cacheinfo()
817 /* Byte 0 is level count, not a descriptor */ in init_intel_cacheinfo()
874 * If cpu_llc_id is not yet set, this means cpuid_level < 4 which in in init_intel_cacheinfo()
878 * c->phys_proc_id. in init_intel_cacheinfo()
881 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; in init_intel_cacheinfo()
884 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); in init_intel_cacheinfo()
898 * For L3, always use the pre-calculated cpu_llc_shared_mask in __cache_amd_cpumap_setup()
904 if (!this_cpu_ci->info_list) in __cache_amd_cpumap_setup()
906 this_leaf = this_cpu_ci->info_list + index; in __cache_amd_cpumap_setup()
911 &this_leaf->shared_cpu_map); in __cache_amd_cpumap_setup()
917 nshared = base->eax.split.num_threads_sharing + 1; in __cache_amd_cpumap_setup()
919 first = apicid - (apicid % nshared); in __cache_amd_cpumap_setup()
920 last = first + nshared - 1; in __cache_amd_cpumap_setup()
924 if (!this_cpu_ci->info_list) in __cache_amd_cpumap_setup()
931 this_leaf = this_cpu_ci->info_list + index; in __cache_amd_cpumap_setup()
938 &this_leaf->shared_cpu_map); in __cache_amd_cpumap_setup()
956 if (c->x86_vendor == X86_VENDOR_AMD || in __cache_cpumap_setup()
957 c->x86_vendor == X86_VENDOR_HYGON) { in __cache_cpumap_setup()
962 this_leaf = this_cpu_ci->info_list + index; in __cache_cpumap_setup()
963 num_threads_sharing = 1 + base->eax.split.num_threads_sharing; in __cache_cpumap_setup()
965 cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); in __cache_cpumap_setup()
972 if (cpu_data(i).apicid >> index_msb == c->apicid >> index_msb) { in __cache_cpumap_setup()
975 if (i == cpu || !sib_cpu_ci->info_list) in __cache_cpumap_setup()
977 sibling_leaf = sib_cpu_ci->info_list + index; in __cache_cpumap_setup()
978 cpumask_set_cpu(i, &this_leaf->shared_cpu_map); in __cache_cpumap_setup()
979 cpumask_set_cpu(cpu, &sibling_leaf->shared_cpu_map); in __cache_cpumap_setup()
986 this_leaf->id = base->id; in ci_leaf_init()
987 this_leaf->attributes = CACHE_ID; in ci_leaf_init()
988 this_leaf->level = base->eax.split.level; in ci_leaf_init()
989 this_leaf->type = cache_type_map[base->eax.split.type]; in ci_leaf_init()
990 this_leaf->coherency_line_size = in ci_leaf_init()
991 base->ebx.split.coherency_line_size + 1; in ci_leaf_init()
992 this_leaf->ways_of_associativity = in ci_leaf_init()
993 base->ebx.split.ways_of_associativity + 1; in ci_leaf_init()
994 this_leaf->size = base->size; in ci_leaf_init()
995 this_leaf->number_of_sets = base->ecx.split.number_of_sets + 1; in ci_leaf_init()
996 this_leaf->physical_line_partition = in ci_leaf_init()
997 base->ebx.split.physical_line_partition + 1; in ci_leaf_init()
998 this_leaf->priv = base->nb; in ci_leaf_init()
1006 return -ENOENT; in init_cache_level()
1008 return -EINVAL; in init_cache_level()
1009 this_cpu_ci->num_levels = 3; in init_cache_level()
1010 this_cpu_ci->num_leaves = num_cache_leaves; in init_cache_level()
1015 * The max shared threads number comes from CPUID.4:EAX[25-14] with input
1025 num_threads_sharing = 1 + id4_regs->eax.split.num_threads_sharing; in get_cache_id()
1027 id4_regs->id = c->apicid >> index_msb; in get_cache_id()
1034 struct cacheinfo *this_leaf = this_cpu_ci->info_list; in populate_cache_leaves()
1037 for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) { in populate_cache_leaves()
1045 this_cpu_ci->cpu_map_populated = true; in populate_cache_leaves()
1075 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ in cache_disable()
1080 * Cache flushing is the most time-consuming step when programming in cache_disable()
1082 * Manual, we can skip it if the processor supports cache self- in cache_disable()
1108 /* Flush TLBs (no need to flush caches - they are disabled) */ in cache_enable()