1 // SPDX-License-Identifier: GPL-2.0
6  *	- Rafael R. Reilova (moved everything from head.S),
8  *	- Channing Corn (tests & fixes),
9  *	- Andrew D. Balsa (code cleanup).
20 #include <asm/spec-ctrl.h>
24 #include <asm/processor-flags.h>
29 #include <asm/intel-family.h>
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
87 	 * When KERNEL_IBRS this MSR is written on return-to-user, unless  in update_spec_ctrl_cond()
205 		hostval = ssbd_tif_to_spec_ctrl(ti->flags);  in x86_virt_spec_ctrl()
234 /* Default mitigation for MDS-affected CPUs */
269 		return -EINVAL;  in mds_cmdline()
294 /* Default mitigation for TAA-affected CPUs */
371 		return -EINVAL;  in tsx_async_abort_parse_cmdline()
432 	 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can  in mmio_select_mitigation()
464 		return -EINVAL;  in mmio_stale_data_parse_cmdline()
527 	 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update  in md_clear_select_mitigation()
624 		return -EINVAL;  in srbds_parse_cmdline()
791 		return -EINVAL;  in gds_parse_cmdline()
833 	 * Consider SMAP to be non-functional as a mitigation on these  in smap_works_speculatively()
852 		 * path of a conditional swapgs with a user-controlled GS  in spectre_v1_select_mitigation()
877 			 * Enable lfences in the kernel entry (non-swapgs)  in spectre_v1_select_mitigation()
936 		return -EINVAL;  in retbleed_parse_cmdline()
947 		} else if (!strcmp(str, "auto")) {  in retbleed_parse_cmdline()
1121 	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";  in spectre_v2_module_string()
1188 	[SPECTRE_V2_USER_STRICT_PREFERRED]	= "User space: Mitigation: STIBP always-on protection",
1198 	{ "auto",		SPECTRE_V2_USER_CMD_AUTO,		false },
1243 	pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);  in spectre_v2_parse_user_cmdline()
1310 			"always-on" : "conditional");  in spectre_v2_user_select_mitigation()
1317 	 * Intel's Enhanced IBRS also protects against cross-thread branch target  in spectre_v2_user_select_mitigation()
1318 	 * injection in user-mode as the IBRS bit remains always set which  in spectre_v2_user_select_mitigation()
1319 	 * implicitly enables cross-thread protections.  However, in legacy IBRS  in spectre_v2_user_select_mitigation()
1322 	 * These modes therefore disable the implicit cross-thread protection,  in spectre_v2_user_select_mitigation()
1333 	 * If STIBP support is not being forced, check if STIBP always-on  in spectre_v2_user_select_mitigation()
1344 			pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");  in spectre_v2_user_select_mitigation()
1378 	{ "auto",		SPECTRE_V2_CMD_AUTO,		  false },
1410 		pr_err("unknown option (%s). Switching to AUTO select\n", arg);  in spectre_v2_parse_cmdline()
1420 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1429 		pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1437 		pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1443 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1449 		pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1455 		pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1461 		pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1481 /* Disable in-kernel use of non-RSB RET predictors */
1513 	 * user-space-poisoned RSB entries.  in spectre_v2_determine_rsb_fill_type_at_vmexit()
1527 			pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");  in spectre_v2_determine_rsb_fill_type_at_vmexit()
1550 	 * If the CPU is not affected and the command line mode is NONE or AUTO  in spectre_v2_select_mitigation()
1647 	 * JMPs gets protection against BHI and Intramode-BTI, but RET  in spectre_v2_select_mitigation()
1648 	 * prediction from a non-RSB predictor is still a risk.  in spectre_v2_select_mitigation()
1667 	 *    which could have a user-poisoned BTB or BHB entry.  in spectre_v2_select_mitigation()
1672 	 *    When IBRS or eIBRS is enabled, the "user -> kernel" attack  in spectre_v2_select_mitigation()
1677 	 *    The "user -> user" attack scenario is mitigated by RSB filling.  in spectre_v2_select_mitigation()
1681 	 *    If the 'next' in-kernel return stack is shorter than 'prev',  in spectre_v2_select_mitigation()
1682 	 *    'next' could be tricked into speculating with a user-poisoned RSB  in spectre_v2_select_mitigation()
1685 	 *    The "user -> kernel" attack scenario is mitigated by SMEP and  in spectre_v2_select_mitigation()
1688 	 *    The "user -> user" scenario, also known as SpectreBHB, requires  in spectre_v2_select_mitigation()
1694 	 * FIXME: Is this pointless for retbleed-affected AMD?  in spectre_v2_select_mitigation()
1709 	 * the CPU supports Enhanced IBRS, kernel might un-intentionally not  in spectre_v2_select_mitigation()
1749 		mask & SPEC_CTRL_STIBP ? "always-on" : "off");  in update_stibp_strict()
1790 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for…
1791 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_ab…
1792 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mm…
1875 	{ "auto",	SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1906 			pr_err("unknown option (%s). Switching to AUTO select\n", arg);  in ssb_parse_cmdline()
1952 	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.  in __ssb_select_mitigation()
1953 	 *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass  in __ssb_select_mitigation()
1954 	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation  in __ssb_select_mitigation()
1992 	 * task, but for a non-current task delay setting the CPU  in task_update_spec_tif()
2006 		return -EPERM;  in l1d_flush_prctl_set()
2010 		set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_prctl_set()
2013 		clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_prctl_set()
2016 		return -ERANGE;  in l1d_flush_prctl_set()
2024 		return -ENXIO;  in ssb_prctl_set()
2030 			return -EPERM;  in ssb_prctl_set()
2048 			return -EPERM;  in ssb_prctl_set()
2054 		return -ERANGE;  in ssb_prctl_set()
2083 		 * updated, unless it was force-disabled by a previous prctl  in ib_prctl_set()
2092 			return -EPERM;  in ib_prctl_set()
2105 			return -EPERM;  in ib_prctl_set()
2118 		return -ERANGE;  in ib_prctl_set()
2134 		return -ENODEV;  in arch_prctl_spec_ctrl_set()
2154 	if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))  in l1d_flush_prctl_get()
2213 		return -ENODEV;  in arch_prctl_spec_ctrl_get()
2232 /* Default mitigation for L1TF-affected CPUs */
2256 	if (c->x86 != 6)  in override_cache_bits()
2259 	switch (c->x86_model) {  in override_cache_bits()
2273 		if (c->x86_cache_bits < 44)  in override_cache_bits()
2274 			c->x86_cache_bits = 44;  in override_cache_bits()
2314 			e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {  in l1tf_select_mitigation()
2319 …pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help y…  in l1tf_select_mitigation()
2332 		return -EINVAL;  in l1tf_cmdline()
2384 		return -EINVAL;  in srso_parse_cmdline()
2390 	else if (!strcmp(str, "safe-ret"))  in srso_parse_cmdline()
2394 	else if (!strcmp(str, "ibpb-vmexit"))  in srso_parse_cmdline()
2403 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html …
2413 		pr_warn("IBPB-extending microcode not applied!\n");  in srso_select_mitigation()
2513 	[VMENTER_L1D_FLUSH_AUTO]		= "auto",
2623 		return ", STIBP: always-on";  in stibp_state()
2636 			return ", IBPB: always-on";  in ibpb_state()
2649 			return ", PBRSB-eIBRS: SW sequence";  in pbrsb_eibrs_state()
2651 			return ", PBRSB-eIBRS: Vulnerable";  in pbrsb_eibrs_state()
2653 		return ", PBRSB-eIBRS: Not affected";  in pbrsb_eibrs_state()
2690 			return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");  in retbleed_show_state()