739 struct x86_pmu {  struct
743 	const char	*name;
744 	int		version;
745 	int		(*handle_irq)(struct pt_regs *);
746 	void		(*disable_all)(void);
747 	void		(*enable_all)(int added);
748 	void		(*enable)(struct perf_event *);
749 	void		(*disable)(struct perf_event *);
750 	void		(*assign)(struct perf_event *event, int idx);
751 	void		(*add)(struct perf_event *);
752 	void		(*del)(struct perf_event *);
753 	void		(*read)(struct perf_event *event);
754 	int		(*set_period)(struct perf_event *event);
755 	u64		(*update)(struct perf_event *event);
756 	int		(*hw_config)(struct perf_event *event);
757 	int		(*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
758 	unsigned	eventsel;
759 	unsigned	perfctr;
760 	int		(*addr_offset)(int index, bool eventsel);
761 	int		(*rdpmc_index)(int index);
762 	u64		(*event_map)(int);
763 	int		max_events;
764 	int		num_counters;
765 	int		num_counters_fixed;
766 	int		cntval_bits;
790 	struct x86_pmu_quirk *quirks;  argument
791 	void		(*limit_period)(struct perf_event *event, s64 *l);
794 	unsigned int	late_ack		:1,
795 			mid_ack			:1,
796 			enabled_ack		:1;
800 	int		attr_rdpmc_broken;
801 	int		attr_rdpmc;
802 	struct attribute **format_attrs;
804 	ssize_t		(*events_sysfs_show)(char *page, u64 config);
805 	const struct attribute_group **attr_update;
807 	unsigned long	attr_freeze_on_smi;
812 	int		(*cpu_prepare)(int cpu);
813 	void		(*cpu_starting)(int cpu);
814 	void		(*cpu_dying)(int cpu);
815 	void		(*cpu_dead)(int cpu);
817 	void		(*check_microcode)(void);
818 	void		(*sched_task)(struct perf_event_pmu_context *pmu_ctx,
824 	u64			intel_ctrl;
825 	union perf_capabilities intel_cap;
830 	unsigned int	bts			:1,
831 			bts_active		:1,
832 			pebs			:1,
833 			pebs_active		:1,
834 			pebs_broken		:1,
835 			pebs_prec_dist		:1,
836 			pebs_no_tlb		:1,
837 			pebs_no_isolation	:1,
838 			pebs_block		:1,
839 			pebs_ept		:1;
840 	int		pebs_record_size;
841 	int		pebs_buffer_size;
842 	int		max_pebs_events;
843 	void		(*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
844 	struct event_constraint *pebs_constraints;
845 	void		(*pebs_aliases)(struct perf_event *event);
846 	u64		(*pebs_latency_data)(struct perf_event *event, u64 status);
847 	unsigned long	large_pebs_flags;
848 	u64		rtm_abort_event;
849 	u64		pebs_capable;
854 	unsigned int	lbr_tos, lbr_from, lbr_to,
855 			lbr_info, lbr_nr;	   /* LBR base regs and size */
856 	union {
860 	union {
864 	bool		lbr_double_abort;	   /* duplicated lbr aborts */
865 	bool		lbr_pt_coexist;		   /* (LBR|BTS) may coexist with PT */
867 	unsigned int	lbr_has_info:1;
868 	unsigned int	lbr_has_tsx:1;
869 	unsigned int	lbr_from_flags:1;
870 	unsigned int	lbr_to_cycles:1;
875 	unsigned int	lbr_depth_mask:8;
876 	unsigned int	lbr_deep_c_reset:1;
877 	unsigned int	lbr_lip:1;
878 	unsigned int	lbr_cpl:1;
879 	unsigned int	lbr_filter:1;
880 	unsigned int	lbr_call_stack:1;
881 	unsigned int	lbr_mispred:1;
882 	unsigned int	lbr_timed_lbr:1;
883 	unsigned int	lbr_br_type:1;
885 	void		(*lbr_reset)(void);
886 	void		(*lbr_read)(struct cpu_hw_events *cpuc);
887 	void		(*lbr_save)(void *ctx);
888 	void		(*lbr_restore)(void *ctx);
893 	atomic_t	lbr_exclusive[x86_lbr_exclusive_max];
898 	int		num_topdown_events;
905 	void		(*swap_task_ctx)(struct perf_event_pmu_context *prev_epc,
911 	unsigned int	amd_nb_constraints : 1;
912 	u64		perf_ctr_pair_en;
937 	 * The global x86_pmu saves the architecture capabilities, which  argument
941 	int				num_hybrid_pmus;
942 	struct x86_hybrid_pmu		*hybrid_pmu;
943 	u8 (*get_hybrid_cpu_type)	(void);