Lines Matching +full:0 +full:x04480000
30 .addr = 0xffe0000c,
32 .mid_rid = 0x21,
35 .addr = 0xffe00014,
37 .mid_rid = 0x22,
40 .addr = 0xffe1000c,
42 .mid_rid = 0x25,
45 .addr = 0xffe10014,
47 .mid_rid = 0x26,
50 .addr = 0xffe2000c,
52 .mid_rid = 0x29,
55 .addr = 0xffe20014,
57 .mid_rid = 0x2a,
60 .addr = 0xa454c098,
62 .mid_rid = 0xb1,
65 .addr = 0xa454c090,
67 .mid_rid = 0xb2,
70 .addr = 0xa454c09c,
72 .mid_rid = 0xb5,
75 .addr = 0xa454c094,
77 .mid_rid = 0xb6,
80 .addr = 0x04ce0030,
82 .mid_rid = 0xc1,
85 .addr = 0x04ce0030,
87 .mid_rid = 0xc2,
93 .offset = 0,
94 .dmars = 0,
95 .dmars_bit = 0,
97 .offset = 0x10,
98 .dmars = 0,
101 .offset = 0x20,
103 .dmars_bit = 0,
105 .offset = 0x30,
109 .offset = 0x50,
111 .dmars_bit = 0,
113 .offset = 0x60,
136 [0] = {
138 .start = 0xfe008020,
139 .end = 0xfe00808f,
144 .start = 0xfe009000,
145 .end = 0xfe00900b,
150 .start = evt2irq(0xbc0),
151 .end = evt2irq(0xbc0),
155 /* IRQ for channels 0-3 */
156 .start = evt2irq(0x800),
157 .end = evt2irq(0x860),
162 .start = evt2irq(0xb80),
163 .end = evt2irq(0xba0),
187 DEFINE_RES_MEM(0xffe00000, 0x100),
188 DEFINE_RES_IRQ(evt2irq(0xc00)),
193 .id = 0,
209 DEFINE_RES_MEM(0xffe10000, 0x100),
210 DEFINE_RES_IRQ(evt2irq(0xc20)),
231 DEFINE_RES_MEM(0xffe20000, 0x100),
232 DEFINE_RES_IRQ(evt2irq(0xc40)),
246 [0] = {
247 .start = 0xa465fec0,
248 .end = 0xa465fec0 + 0x58 - 1,
253 .start = evt2irq(0x7a0),
258 .start = evt2irq(0x7c0),
263 .start = evt2irq(0x780),
280 [0] = {
282 .start = 0x04480000,
283 .end = 0x044800FF,
287 .start = evt2irq(0xa20),
288 .end = evt2irq(0xa20),
295 .id = 0, /* "usbf0" clock */
298 .coherent_dma_mask = 0xffffffff,
306 [0] = {
308 .start = 0x04470000,
309 .end = 0x04470017,
313 .start = evt2irq(0xe00),
314 .end = evt2irq(0xe60),
321 .id = 0, /* "i2c0" clock */
328 .version = "0",
329 .irq = evt2irq(0x980),
333 [0] = {
335 .start = 0xfe900000,
336 .end = 0xfe9022eb,
346 .id = 0,
356 .version = "0",
357 .irq = evt2irq(0x8c0),
361 [0] = {
363 .start = 0xfe920000,
364 .end = 0xfe9200b7,
384 .version = "0",
385 .irq = evt2irq(0x560),
389 [0] = {
391 .start = 0xfea00000,
392 .end = 0xfea102d3,
411 .channels_mask = 0x20,
415 DEFINE_RES_MEM(0x044a0000, 0x70),
416 DEFINE_RES_IRQ(evt2irq(0xf00)),
421 .id = 0,
434 DEFINE_RES_MEM(0xffd80000, 0x2c),
435 DEFINE_RES_IRQ(evt2irq(0x400)),
436 DEFINE_RES_IRQ(evt2irq(0x420)),
437 DEFINE_RES_IRQ(evt2irq(0x440)),
442 .id = 0,
458 [0] = {
459 .start = 0xa4540000,
460 .end = 0xa454c10f,
464 .start = evt2irq(0xf80),
521 UNUSED=0,
548 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
549 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
550 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
551 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
552 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
553 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
554 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
555 INTC_VECT(RTC_CUI, 0x7c0),
556 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
557 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
558 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
559 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
560 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
561 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
562 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
563 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
564 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
565 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
566 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
567 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
568 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
569 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
570 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
571 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
572 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
573 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
574 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
575 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
576 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
577 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
593 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
595 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
597 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
598 { 0, 0, 0, VPU, } },
599 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
600 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
601 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
602 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
603 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
604 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
605 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
606 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
607 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
610 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
611 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
612 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
613 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
614 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
616 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
617 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
618 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
623 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
624 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
625 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
626 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
627 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
628 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
629 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
630 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
631 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
632 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
633 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
634 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
635 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
640 { 0xa414001c, 16, 2, /* ICR1 */
645 { 0xa4140024, 0, 8, /* INTREQ00 */
665 setup_bootmem_node(1, 0x055f0000, 0x05610000); in plat_mem_setup()