Lines Matching +full:0 +full:x700
23 DEFINE_RES_MEM(0xffe80000, 0x100),
24 DEFINE_RES_IRQ(evt2irq(0x700)),
25 DEFINE_RES_IRQ(evt2irq(0x720)),
26 DEFINE_RES_IRQ(evt2irq(0x760)),
27 DEFINE_RES_IRQ(evt2irq(0x740)),
32 .id = 0,
45 DEFINE_RES_MEM(0xffd80000, 0x30),
46 DEFINE_RES_IRQ(evt2irq(0x400)),
47 DEFINE_RES_IRQ(evt2irq(0x420)),
48 DEFINE_RES_IRQ(evt2irq(0x440)),
53 .id = 0,
85 UNUSED = 0,
93 INTC_VECT(HUDI, 0x600),
94 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
95 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
96 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
97 INTC_VECT(RTC, 0x4c0),
98 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
99 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
100 INTC_VECT(WDT, 0x560),
104 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
106 { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
107 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
114 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
115 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
126 #define INTC_ICR 0xffd00000UL
132 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ in plat_irq_setup_pins()