Lines Matching full:v1
100 * V1..V4: Data for CRC computation.
132 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
133 VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
138 VX %v1,%v0,%v1 /* V1 ^= CRC */
154 * Perform a GF(2) multiplication of the doublewords in V1 with
157 * stored in V1. Repeat this step for the register contents
160 VGFMAG %v1,CONST_R2R1,%v1,%v5
173 * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3
177 VGFMAG %v1,CONST_R4R3,%v1,%v2
178 VGFMAG %v1,CONST_R4R3,%v1,%v3
179 VGFMAG %v1,CONST_R4R3,%v1,%v4
188 VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
214 * Compute GF(2) product of V1 and V0. The rightmost doubleword
215 * of V1 is multiplied with R4. The leftmost doubleword of V1 is
219 VGFMG %v1,%v0,%v1
223 * in V1 with R5 and XOR the result with the remaining bits in V1.
225 * To achieve this by a single VGFMAG, right shift V1 by a word
228 * doubleword into the rightmost doubleword element of V1; the other
232 * the leftmost product of V1.
235 VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */
236 VUPLLF %v1,%v1 /* Split rightmost doubleword */
237 VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */
243 * in V1 (R(x)), degree-32 generator polynomial, and the reduction
259 VUPLLF %v2,%v1
264 * V2 and XOR the intermediate result, T2(x), with the value in V1.
268 VGFMAG %v2,CONST_CRC_POLY,%v2,%v1