Lines Matching +full:off +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0
20 u32 state; member
46 if (!irq || aplic->nr_irqs <= irq) in aplic_read_sourcecfg()
48 irqd = &aplic->irqs[irq]; in aplic_read_sourcecfg()
50 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_read_sourcecfg()
51 ret = irqd->sourcecfg; in aplic_read_sourcecfg()
52 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_read_sourcecfg()
62 if (!irq || aplic->nr_irqs <= irq) in aplic_write_sourcecfg()
64 irqd = &aplic->irqs[irq]; in aplic_write_sourcecfg()
71 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_write_sourcecfg()
72 irqd->sourcecfg = val; in aplic_write_sourcecfg()
73 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_write_sourcecfg()
82 if (!irq || aplic->nr_irqs <= irq) in aplic_read_target()
84 irqd = &aplic->irqs[irq]; in aplic_read_target()
86 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_read_target()
87 ret = irqd->target; in aplic_read_target()
88 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_read_target()
98 if (!irq || aplic->nr_irqs <= irq) in aplic_write_target()
100 irqd = &aplic->irqs[irq]; in aplic_write_target()
106 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_write_target()
107 irqd->target = val; in aplic_write_target()
108 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_write_target()
117 if (!irq || aplic->nr_irqs <= irq) in aplic_read_pending()
119 irqd = &aplic->irqs[irq]; in aplic_read_pending()
121 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_read_pending()
122 ret = (irqd->state & APLIC_IRQ_STATE_PENDING) ? true : false; in aplic_read_pending()
123 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_read_pending()
133 if (!irq || aplic->nr_irqs <= irq) in aplic_write_pending()
135 irqd = &aplic->irqs[irq]; in aplic_write_pending()
137 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_write_pending()
139 sm = irqd->sourcecfg & APLIC_SOURCECFG_SM_MASK; in aplic_write_pending()
146 irqd->state |= APLIC_IRQ_STATE_PENDING; in aplic_write_pending()
148 irqd->state &= ~APLIC_IRQ_STATE_PENDING; in aplic_write_pending()
151 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_write_pending()
160 if (!irq || aplic->nr_irqs <= irq) in aplic_read_enabled()
162 irqd = &aplic->irqs[irq]; in aplic_read_enabled()
164 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_read_enabled()
165 ret = (irqd->state & APLIC_IRQ_STATE_ENABLED) ? true : false; in aplic_read_enabled()
166 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_read_enabled()
176 if (!irq || aplic->nr_irqs <= irq) in aplic_write_enabled()
178 irqd = &aplic->irqs[irq]; in aplic_write_enabled()
180 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_write_enabled()
182 irqd->state |= APLIC_IRQ_STATE_ENABLED; in aplic_write_enabled()
184 irqd->state &= ~APLIC_IRQ_STATE_ENABLED; in aplic_write_enabled()
185 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_write_enabled()
194 if (!irq || aplic->nr_irqs <= irq) in aplic_read_input()
196 irqd = &aplic->irqs[irq]; in aplic_read_input()
198 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_read_input()
199 ret = (irqd->state & APLIC_IRQ_STATE_INPUT) ? true : false; in aplic_read_input()
200 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_read_input()
223 struct aplic *aplic = kvm->arch.aia.aplic_state; in aplic_update_irq_range()
225 if (!(aplic->domaincfg & APLIC_DOMAINCFG_IE)) in aplic_update_irq_range()
229 if (!irq || aplic->nr_irqs <= irq) in aplic_update_irq_range()
231 irqd = &aplic->irqs[irq]; in aplic_update_irq_range()
233 raw_spin_lock_irqsave(&irqd->lock, flags); in aplic_update_irq_range()
236 target = irqd->target; in aplic_update_irq_range()
237 if ((irqd->state & APLIC_IRQ_STATE_ENPEND) == in aplic_update_irq_range()
239 irqd->state &= ~APLIC_IRQ_STATE_PENDING; in aplic_update_irq_range()
243 raw_spin_unlock_irqrestore(&irqd->lock, flags); in aplic_update_irq_range()
256 struct aplic *aplic = kvm->arch.aia.aplic_state; in kvm_riscv_aia_aplic_inject()
258 if (!aplic || !source || (aplic->nr_irqs <= source)) in kvm_riscv_aia_aplic_inject()
259 return -ENODEV; in kvm_riscv_aia_aplic_inject()
260 irqd = &aplic->irqs[source]; in kvm_riscv_aia_aplic_inject()
261 ie = (aplic->domaincfg & APLIC_DOMAINCFG_IE) ? true : false; in kvm_riscv_aia_aplic_inject()
263 raw_spin_lock_irqsave(&irqd->lock, flags); in kvm_riscv_aia_aplic_inject()
265 if (irqd->sourcecfg & APLIC_SOURCECFG_D) in kvm_riscv_aia_aplic_inject()
268 switch (irqd->sourcecfg & APLIC_SOURCECFG_SM_MASK) { in kvm_riscv_aia_aplic_inject()
270 if (level && !(irqd->state & APLIC_IRQ_STATE_INPUT) && in kvm_riscv_aia_aplic_inject()
271 !(irqd->state & APLIC_IRQ_STATE_PENDING)) in kvm_riscv_aia_aplic_inject()
272 irqd->state |= APLIC_IRQ_STATE_PENDING; in kvm_riscv_aia_aplic_inject()
275 if (!level && (irqd->state & APLIC_IRQ_STATE_INPUT) && in kvm_riscv_aia_aplic_inject()
276 !(irqd->state & APLIC_IRQ_STATE_PENDING)) in kvm_riscv_aia_aplic_inject()
277 irqd->state |= APLIC_IRQ_STATE_PENDING; in kvm_riscv_aia_aplic_inject()
280 if (level && !(irqd->state & APLIC_IRQ_STATE_PENDING)) in kvm_riscv_aia_aplic_inject()
281 irqd->state |= APLIC_IRQ_STATE_PENDING; in kvm_riscv_aia_aplic_inject()
284 if (!level && !(irqd->state & APLIC_IRQ_STATE_PENDING)) in kvm_riscv_aia_aplic_inject()
285 irqd->state |= APLIC_IRQ_STATE_PENDING; in kvm_riscv_aia_aplic_inject()
290 irqd->state |= APLIC_IRQ_STATE_INPUT; in kvm_riscv_aia_aplic_inject()
292 irqd->state &= ~APLIC_IRQ_STATE_INPUT; in kvm_riscv_aia_aplic_inject()
294 target = irqd->target; in kvm_riscv_aia_aplic_inject()
295 if (ie && ((irqd->state & APLIC_IRQ_STATE_ENPEND) == in kvm_riscv_aia_aplic_inject()
297 irqd->state &= ~APLIC_IRQ_STATE_PENDING; in kvm_riscv_aia_aplic_inject()
302 raw_spin_unlock_irqrestore(&irqd->lock, flags); in kvm_riscv_aia_aplic_inject()
362 static int aplic_mmio_read_offset(struct kvm *kvm, gpa_t off, u32 *val32) in aplic_mmio_read_offset() argument
365 struct aplic *aplic = kvm->arch.aia.aplic_state; in aplic_mmio_read_offset()
367 if ((off & 0x3) != 0) in aplic_mmio_read_offset()
368 return -EOPNOTSUPP; in aplic_mmio_read_offset()
370 if (off == APLIC_DOMAINCFG) { in aplic_mmio_read_offset()
372 aplic->domaincfg | APLIC_DOMAINCFG_DM; in aplic_mmio_read_offset()
373 } else if ((off >= APLIC_SOURCECFG_BASE) && in aplic_mmio_read_offset()
374 (off < (APLIC_SOURCECFG_BASE + (aplic->nr_irqs - 1) * 4))) { in aplic_mmio_read_offset()
375 i = ((off - APLIC_SOURCECFG_BASE) >> 2) + 1; in aplic_mmio_read_offset()
377 } else if ((off >= APLIC_SETIP_BASE) && in aplic_mmio_read_offset()
378 (off < (APLIC_SETIP_BASE + aplic->nr_words * 4))) { in aplic_mmio_read_offset()
379 i = (off - APLIC_SETIP_BASE) >> 2; in aplic_mmio_read_offset()
381 } else if (off == APLIC_SETIPNUM) { in aplic_mmio_read_offset()
383 } else if ((off >= APLIC_CLRIP_BASE) && in aplic_mmio_read_offset()
384 (off < (APLIC_CLRIP_BASE + aplic->nr_words * 4))) { in aplic_mmio_read_offset()
385 i = (off - APLIC_CLRIP_BASE) >> 2; in aplic_mmio_read_offset()
387 } else if (off == APLIC_CLRIPNUM) { in aplic_mmio_read_offset()
389 } else if ((off >= APLIC_SETIE_BASE) && in aplic_mmio_read_offset()
390 (off < (APLIC_SETIE_BASE + aplic->nr_words * 4))) { in aplic_mmio_read_offset()
391 i = (off - APLIC_SETIE_BASE) >> 2; in aplic_mmio_read_offset()
393 } else if (off == APLIC_SETIENUM) { in aplic_mmio_read_offset()
395 } else if ((off >= APLIC_CLRIE_BASE) && in aplic_mmio_read_offset()
396 (off < (APLIC_CLRIE_BASE + aplic->nr_words * 4))) { in aplic_mmio_read_offset()
398 } else if (off == APLIC_CLRIENUM) { in aplic_mmio_read_offset()
400 } else if (off == APLIC_SETIPNUM_LE) { in aplic_mmio_read_offset()
402 } else if (off == APLIC_SETIPNUM_BE) { in aplic_mmio_read_offset()
404 } else if (off == APLIC_GENMSI) { in aplic_mmio_read_offset()
405 *val32 = aplic->genmsi; in aplic_mmio_read_offset()
406 } else if ((off >= APLIC_TARGET_BASE) && in aplic_mmio_read_offset()
407 (off < (APLIC_TARGET_BASE + (aplic->nr_irqs - 1) * 4))) { in aplic_mmio_read_offset()
408 i = ((off - APLIC_TARGET_BASE) >> 2) + 1; in aplic_mmio_read_offset()
411 return -ENODEV; in aplic_mmio_read_offset()
420 return -EOPNOTSUPP; in aplic_mmio_read()
422 return aplic_mmio_read_offset(vcpu->kvm, in aplic_mmio_read()
423 addr - vcpu->kvm->arch.aia.aplic_addr, in aplic_mmio_read()
427 static int aplic_mmio_write_offset(struct kvm *kvm, gpa_t off, u32 val32) in aplic_mmio_write_offset() argument
430 struct aplic *aplic = kvm->arch.aia.aplic_state; in aplic_mmio_write_offset()
432 if ((off & 0x3) != 0) in aplic_mmio_write_offset()
433 return -EOPNOTSUPP; in aplic_mmio_write_offset()
435 if (off == APLIC_DOMAINCFG) { in aplic_mmio_write_offset()
437 aplic->domaincfg = val32 & APLIC_DOMAINCFG_IE; in aplic_mmio_write_offset()
438 } else if ((off >= APLIC_SOURCECFG_BASE) && in aplic_mmio_write_offset()
439 (off < (APLIC_SOURCECFG_BASE + (aplic->nr_irqs - 1) * 4))) { in aplic_mmio_write_offset()
440 i = ((off - APLIC_SOURCECFG_BASE) >> 2) + 1; in aplic_mmio_write_offset()
442 } else if ((off >= APLIC_SETIP_BASE) && in aplic_mmio_write_offset()
443 (off < (APLIC_SETIP_BASE + aplic->nr_words * 4))) { in aplic_mmio_write_offset()
444 i = (off - APLIC_SETIP_BASE) >> 2; in aplic_mmio_write_offset()
446 } else if (off == APLIC_SETIPNUM) { in aplic_mmio_write_offset()
448 } else if ((off >= APLIC_CLRIP_BASE) && in aplic_mmio_write_offset()
449 (off < (APLIC_CLRIP_BASE + aplic->nr_words * 4))) { in aplic_mmio_write_offset()
450 i = (off - APLIC_CLRIP_BASE) >> 2; in aplic_mmio_write_offset()
452 } else if (off == APLIC_CLRIPNUM) { in aplic_mmio_write_offset()
454 } else if ((off >= APLIC_SETIE_BASE) && in aplic_mmio_write_offset()
455 (off < (APLIC_SETIE_BASE + aplic->nr_words * 4))) { in aplic_mmio_write_offset()
456 i = (off - APLIC_SETIE_BASE) >> 2; in aplic_mmio_write_offset()
458 } else if (off == APLIC_SETIENUM) { in aplic_mmio_write_offset()
460 } else if ((off >= APLIC_CLRIE_BASE) && in aplic_mmio_write_offset()
461 (off < (APLIC_CLRIE_BASE + aplic->nr_words * 4))) { in aplic_mmio_write_offset()
462 i = (off - APLIC_CLRIE_BASE) >> 2; in aplic_mmio_write_offset()
464 } else if (off == APLIC_CLRIENUM) { in aplic_mmio_write_offset()
466 } else if (off == APLIC_SETIPNUM_LE) { in aplic_mmio_write_offset()
468 } else if (off == APLIC_SETIPNUM_BE) { in aplic_mmio_write_offset()
470 } else if (off == APLIC_GENMSI) { in aplic_mmio_write_offset()
471 aplic->genmsi = val32 & ~(APLIC_TARGET_GUEST_IDX_MASK << in aplic_mmio_write_offset()
476 } else if ((off >= APLIC_TARGET_BASE) && in aplic_mmio_write_offset()
477 (off < (APLIC_TARGET_BASE + (aplic->nr_irqs - 1) * 4))) { in aplic_mmio_write_offset()
478 i = ((off - APLIC_TARGET_BASE) >> 2) + 1; in aplic_mmio_write_offset()
481 return -ENODEV; in aplic_mmio_write_offset()
483 aplic_update_irq_range(kvm, 1, aplic->nr_irqs - 1); in aplic_mmio_write_offset()
492 return -EOPNOTSUPP; in aplic_mmio_write()
494 return aplic_mmio_write_offset(vcpu->kvm, in aplic_mmio_write()
495 addr - vcpu->kvm->arch.aia.aplic_addr, in aplic_mmio_write()
508 if (!kvm->arch.aia.aplic_state) in kvm_riscv_aia_aplic_set_attr()
509 return -ENODEV; in kvm_riscv_aia_aplic_set_attr()
522 if (!kvm->arch.aia.aplic_state) in kvm_riscv_aia_aplic_get_attr()
523 return -ENODEV; in kvm_riscv_aia_aplic_get_attr()
537 if (!kvm->arch.aia.aplic_state) in kvm_riscv_aia_aplic_has_attr()
538 return -ENODEV; in kvm_riscv_aia_aplic_has_attr()
553 if (!kvm->arch.aia.nr_sources) in kvm_riscv_aia_aplic_init()
556 /* Allocate APLIC global state */ in kvm_riscv_aia_aplic_init()
559 return -ENOMEM; in kvm_riscv_aia_aplic_init()
560 kvm->arch.aia.aplic_state = aplic; in kvm_riscv_aia_aplic_init()
563 aplic->nr_irqs = kvm->arch.aia.nr_sources + 1; in kvm_riscv_aia_aplic_init()
564 aplic->nr_words = DIV_ROUND_UP(aplic->nr_irqs, 32); in kvm_riscv_aia_aplic_init()
565 aplic->irqs = kcalloc(aplic->nr_irqs, in kvm_riscv_aia_aplic_init()
566 sizeof(*aplic->irqs), GFP_KERNEL); in kvm_riscv_aia_aplic_init()
567 if (!aplic->irqs) { in kvm_riscv_aia_aplic_init()
568 ret = -ENOMEM; in kvm_riscv_aia_aplic_init()
571 for (i = 0; i < aplic->nr_irqs; i++) in kvm_riscv_aia_aplic_init()
572 raw_spin_lock_init(&aplic->irqs[i].lock); in kvm_riscv_aia_aplic_init()
575 kvm_iodevice_init(&aplic->iodev, &aplic_iodoev_ops); in kvm_riscv_aia_aplic_init()
576 mutex_lock(&kvm->slots_lock); in kvm_riscv_aia_aplic_init()
578 kvm->arch.aia.aplic_addr, in kvm_riscv_aia_aplic_init()
580 &aplic->iodev); in kvm_riscv_aia_aplic_init()
581 mutex_unlock(&kvm->slots_lock); in kvm_riscv_aia_aplic_init()
586 ret = kvm_riscv_setup_default_irq_routing(kvm, aplic->nr_irqs); in kvm_riscv_aia_aplic_init()
593 mutex_lock(&kvm->slots_lock); in kvm_riscv_aia_aplic_init()
594 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &aplic->iodev); in kvm_riscv_aia_aplic_init()
595 mutex_unlock(&kvm->slots_lock); in kvm_riscv_aia_aplic_init()
597 kfree(aplic->irqs); in kvm_riscv_aia_aplic_init()
599 kvm->arch.aia.aplic_state = NULL; in kvm_riscv_aia_aplic_init()
606 struct aplic *aplic = kvm->arch.aia.aplic_state; in kvm_riscv_aia_aplic_cleanup()
611 mutex_lock(&kvm->slots_lock); in kvm_riscv_aia_aplic_cleanup()
612 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &aplic->iodev); in kvm_riscv_aia_aplic_cleanup()
613 mutex_unlock(&kvm->slots_lock); in kvm_riscv_aia_aplic_cleanup()
615 kfree(aplic->irqs); in kvm_riscv_aia_aplic_cleanup()
617 kvm->arch.aia.aplic_state = NULL; in kvm_riscv_aia_aplic_cleanup()