Lines Matching +full:reg +full:- +full:io +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
23 reg = <0>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
27 d-cache-block-size = <64>;
28 d-cache-size = <65536>;
29 d-cache-sets = <512>;
30 next-level-cache = <&l2_cache>;
31 mmu-type = "riscv,sv39";
33 cpu0_intc: interrupt-controller {
34 compatible = "riscv,cpu-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
44 reg = <1>;
45 i-cache-block-size = <64>;
46 i-cache-size = <65536>;
47 i-cache-sets = <512>;
48 d-cache-block-size = <64>;
49 d-cache-size = <65536>;
50 d-cache-sets = <512>;
51 next-level-cache = <&l2_cache>;
52 mmu-type = "riscv,sv39";
54 cpu1_intc: interrupt-controller {
55 compatible = "riscv,cpu-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
65 reg = <2>;
66 i-cache-block-size = <64>;
67 i-cache-size = <65536>;
68 i-cache-sets = <512>;
69 d-cache-block-size = <64>;
70 d-cache-size = <65536>;
71 d-cache-sets = <512>;
72 next-level-cache = <&l2_cache>;
73 mmu-type = "riscv,sv39";
75 cpu2_intc: interrupt-controller {
76 compatible = "riscv,cpu-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
86 reg = <3>;
87 i-cache-block-size = <64>;
88 i-cache-size = <65536>;
89 i-cache-sets = <512>;
90 d-cache-block-size = <64>;
91 d-cache-size = <65536>;
92 d-cache-sets = <512>;
93 next-level-cache = <&l2_cache>;
94 mmu-type = "riscv,sv39";
96 cpu3_intc: interrupt-controller {
97 compatible = "riscv,cpu-intc";
98 interrupt-controller;
99 #interrupt-cells = <1>;
103 l2_cache: l2-cache {
105 cache-block-size = <64>;
106 cache-level = <2>;
107 cache-size = <1048576>;
108 cache-sets = <1024>;
109 cache-unified;
114 compatible = "fixed-clock";
115 clock-output-names = "osc_24m";
116 #clock-cells = <0>;
119 osc_32k: 32k-oscillator {
120 compatible = "fixed-clock";
121 clock-output-names = "osc_32k";
122 #clock-cells = <0>;
125 apb_clk: apb-clk-clock {
126 compatible = "fixed-clock";
127 clock-output-names = "apb_clk";
128 #clock-cells = <0>;
131 uart_sclk: uart-sclk-clock {
132 compatible = "fixed-clock";
133 clock-output-names = "uart_sclk";
134 #clock-cells = <0>;
138 compatible = "simple-bus";
139 interrupt-parent = <&plic>;
140 #address-cells = <2>;
141 #size-cells = <2>;
142 dma-noncoherent;
145 plic: interrupt-controller@ffd8000000 {
146 compatible = "thead,th1520-plic", "thead,c900-plic";
147 reg = <0xff 0xd8000000 0x0 0x01000000>;
148 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
152 interrupt-controller;
153 #address-cells = <0>;
154 #interrupt-cells = <2>;
159 compatible = "thead,th1520-clint", "thead,c900-clint";
160 reg = <0xff 0xdc000000 0x0 0x00010000>;
161 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
168 compatible = "snps,dw-apb-uart";
169 reg = <0xff 0xe7014000 0x0 0x100>;
172 reg-shift = <2>;
173 reg-io-width = <4>;
178 compatible = "snps,dw-apb-uart";
179 reg = <0xff 0xe7f00000 0x0 0x100>;
182 reg-shift = <2>;
183 reg-io-width = <4>;
188 compatible = "snps,dw-apb-uart";
189 reg = <0xff 0xe7f04000 0x0 0x100>;
192 reg-shift = <2>;
193 reg-io-width = <4>;
198 compatible = "snps,dw-apb-gpio";
199 reg = <0xff 0xe7f34000 0x0 0x1000>;
200 #address-cells = <1>;
201 #size-cells = <0>;
203 portc: gpio-controller@0 {
204 compatible = "snps,dw-apb-gpio-port";
205 gpio-controller;
206 #gpio-cells = <2>;
208 reg = <0>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
216 compatible = "snps,dw-apb-gpio";
217 reg = <0xff 0xe7f38000 0x0 0x1000>;
218 #address-cells = <1>;
219 #size-cells = <0>;
221 portd: gpio-controller@0 {
222 compatible = "snps,dw-apb-gpio-port";
223 gpio-controller;
224 #gpio-cells = <2>;
226 reg = <0>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
234 compatible = "snps,dw-apb-gpio";
235 reg = <0xff 0xec005000 0x0 0x1000>;
236 #address-cells = <1>;
237 #size-cells = <0>;
239 porta: gpio-controller@0 {
240 compatible = "snps,dw-apb-gpio-port";
241 gpio-controller;
242 #gpio-cells = <2>;
244 reg = <0>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
252 compatible = "snps,dw-apb-gpio";
253 reg = <0xff 0xec006000 0x0 0x1000>;
254 #address-cells = <1>;
255 #size-cells = <0>;
257 portb: gpio-controller@0 {
258 compatible = "snps,dw-apb-gpio-port";
259 gpio-controller;
260 #gpio-cells = <2>;
262 reg = <0>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
270 compatible = "snps,dw-apb-uart";
271 reg = <0xff 0xec010000 0x0 0x4000>;
274 reg-shift = <2>;
275 reg-io-width = <4>;
279 dmac0: dma-controller@ffefc00000 {
280 compatible = "snps,axi-dma-1.01a";
281 reg = <0xff 0xefc00000 0x0 0x1000>;
284 clock-names = "core-clk", "cfgr-clk";
285 #dma-cells = <1>;
286 dma-channels = <4>;
287 snps,block-size = <65536 65536 65536 65536>;
289 snps,dma-masters = <1>;
290 snps,data-width = <4>;
291 snps,axi-max-burst-len = <16>;
296 compatible = "snps,dw-apb-timer";
297 reg = <0xff 0xefc32000 0x0 0x14>;
299 clock-names = "timer";
305 compatible = "snps,dw-apb-timer";
306 reg = <0xff 0xefc32014 0x0 0x14>;
308 clock-names = "timer";
314 compatible = "snps,dw-apb-timer";
315 reg = <0xff 0xefc32028 0x0 0x14>;
317 clock-names = "timer";
323 compatible = "snps,dw-apb-timer";
324 reg = <0xff 0xefc3203c 0x0 0x14>;
326 clock-names = "timer";
332 compatible = "snps,dw-apb-uart";
333 reg = <0xff 0xf7f08000 0x0 0x4000>;
336 reg-shift = <2>;
337 reg-io-width = <4>;
342 compatible = "snps,dw-apb-uart";
343 reg = <0xff 0xf7f0c000 0x0 0x4000>;
346 reg-shift = <2>;
347 reg-io-width = <4>;
352 compatible = "snps,dw-apb-timer";
353 reg = <0xff 0xffc33000 0x0 0x14>;
355 clock-names = "timer";
361 compatible = "snps,dw-apb-timer";
362 reg = <0xff 0xffc33014 0x0 0x14>;
364 clock-names = "timer";
370 compatible = "snps,dw-apb-timer";
371 reg = <0xff 0xffc33028 0x0 0x14>;
373 clock-names = "timer";
379 compatible = "snps,dw-apb-timer";
380 reg = <0xff 0xffc3303c 0x0 0x14>;
382 clock-names = "timer";
388 compatible = "snps,dw-apb-gpio";
389 reg = <0xff 0xfff41000 0x0 0x1000>;
390 #address-cells = <1>;
391 #size-cells = <0>;
393 porte: gpio-controller@0 {
394 compatible = "snps,dw-apb-gpio-port";
395 gpio-controller;
396 #gpio-cells = <2>;
398 reg = <0>;
399 interrupt-controller;
400 #interrupt-cells = <2>;
406 compatible = "snps,dw-apb-gpio";
407 reg = <0xff 0xfff52000 0x0 0x1000>;
408 #address-cells = <1>;
409 #size-cells = <0>;
411 portf: gpio-controller@0 {
412 compatible = "snps,dw-apb-gpio-port";
413 gpio-controller;
414 #gpio-cells = <2>;
416 reg = <0>;
417 interrupt-controller;
418 #interrupt-cells = <2>;