Lines Matching refs:SH
622 #define SH SE_SDW + 1 macro
625 #define EVUIMM SH
627 #define FC SH
631 #define HTM_SI SH + 1
4587 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4588 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4590 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4591 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4593 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4595 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4597 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4599 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4600 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4973 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
4974 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
5059 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5060 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
5933 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5934 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
6012 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6013 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
6077 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6078 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6079 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6080 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6205 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6206 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
7106 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7107 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7155 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7156 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7166 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7167 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7176 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7177 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},