Lines Matching refs:CACHE_EVENT_PTR
159 CACHE_EVENT_PTR(PM_LD_MISS_L1),
160 CACHE_EVENT_PTR(PM_LD_REF_L1),
161 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
162 CACHE_EVENT_PTR(PM_ST_MISS_L1),
163 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
164 CACHE_EVENT_PTR(PM_INST_FROM_L1),
165 CACHE_EVENT_PTR(PM_IC_PREF_REQ),
166 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
167 CACHE_EVENT_PTR(PM_DATA_FROM_L3),
168 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
169 CACHE_EVENT_PTR(PM_BR_CMPL),
170 CACHE_EVENT_PTR(PM_DTLB_MISS),
171 CACHE_EVENT_PTR(PM_ITLB_MISS),
184 CACHE_EVENT_PTR(PM_LD_MISS_L1),
185 CACHE_EVENT_PTR(PM_LD_REF_L1),
186 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
187 CACHE_EVENT_PTR(PM_ST_MISS_L1),
188 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
189 CACHE_EVENT_PTR(PM_INST_FROM_L1),
190 CACHE_EVENT_PTR(PM_IC_PREF_REQ),
191 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
192 CACHE_EVENT_PTR(PM_DATA_FROM_L3),
193 CACHE_EVENT_PTR(PM_L3_PF_MISS_L3),
194 CACHE_EVENT_PTR(PM_L2_ST_MISS),
195 CACHE_EVENT_PTR(PM_L2_ST),
196 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
197 CACHE_EVENT_PTR(PM_BR_CMPL),
198 CACHE_EVENT_PTR(PM_DTLB_MISS),
199 CACHE_EVENT_PTR(PM_ITLB_MISS),