19 	u64 msr = vcpu->arch.shregs.msr;  in emulate_tx_failure()
21 	tfiar = vcpu->arch.regs.nip & ~0x3ull;  in emulate_tx_failure()
23 	if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))  in emulate_tx_failure()
29 	vcpu->arch.tfiar = tfiar;  in emulate_tx_failure()
31 	vcpu->arch.texasr = (vcpu->arch.texasr & 0x3ffffff) | texasr;  in emulate_tx_failure()
37  * instruction image is in vcpu->arch.emul_inst.  If the guest was in
44 	u32 instr = vcpu->arch.emul_inst;  in kvmhv_p9_tm_emulation()
45 	u64 msr = vcpu->arch.shregs.msr;  in kvmhv_p9_tm_emulation()
56 	vcpu->arch.regs.nip -= 4;  in kvmhv_p9_tm_emulation()
72 		newmsr = vcpu->arch.shregs.srr1;  in kvmhv_p9_tm_emulation()
78 		vcpu->arch.shregs.msr = newmsr;  in kvmhv_p9_tm_emulation()
79 		vcpu->arch.cfar = vcpu->arch.regs.nip;  in kvmhv_p9_tm_emulation()
80 		vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;  in kvmhv_p9_tm_emulation()
84 		if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {  in kvmhv_p9_tm_emulation()
90 		if (!(vcpu->arch.hfscr & HFSCR_EBB)) {  in kvmhv_p9_tm_emulation()
91 			vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
92 			vcpu->arch.hfscr |= (u64)FSCR_EBB_LG << 56;  in kvmhv_p9_tm_emulation()
93 			vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;  in kvmhv_p9_tm_emulation()
96 		if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {  in kvmhv_p9_tm_emulation()
98 			vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
99 			vcpu->arch.fscr |= (u64)FSCR_EBB_LG << 56;  in kvmhv_p9_tm_emulation()
103 		bescr = vcpu->arch.bescr;  in kvmhv_p9_tm_emulation()
110 		vcpu->arch.bescr = bescr;  in kvmhv_p9_tm_emulation()
112 		vcpu->arch.shregs.msr = msr;  in kvmhv_p9_tm_emulation()
113 		vcpu->arch.cfar = vcpu->arch.regs.nip;  in kvmhv_p9_tm_emulation()
114 		vcpu->arch.regs.nip = vcpu->arch.ebbrr;  in kvmhv_p9_tm_emulation()
128 		vcpu->arch.shregs.msr = newmsr;  in kvmhv_p9_tm_emulation()
129 		vcpu->arch.regs.nip += 4;  in kvmhv_p9_tm_emulation()
134 		/* check for PR=1 and arch 2.06 bit set in PCR */  in kvmhv_p9_tm_emulation()
135 		if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {  in kvmhv_p9_tm_emulation()
141 		if (!(vcpu->arch.hfscr & HFSCR_TM)) {  in kvmhv_p9_tm_emulation()
142 			vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
143 			vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;  in kvmhv_p9_tm_emulation()
144 			vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;  in kvmhv_p9_tm_emulation()
149 			vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
150 			vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;  in kvmhv_p9_tm_emulation()
156 		vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |  in kvmhv_p9_tm_emulation()
166 		vcpu->arch.shregs.msr = msr;  in kvmhv_p9_tm_emulation()
167 		vcpu->arch.regs.nip += 4;  in kvmhv_p9_tm_emulation()
173 		if (!(vcpu->arch.hfscr & HFSCR_TM)) {  in kvmhv_p9_tm_emulation()
174 			vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
175 			vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;  in kvmhv_p9_tm_emulation()
176 			vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;  in kvmhv_p9_tm_emulation()
181 			vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
182 			vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;  in kvmhv_p9_tm_emulation()
193 		if (!(vcpu->arch.orig_texasr & TEXASR_FS)) {  in kvmhv_p9_tm_emulation()
203 		vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |  in kvmhv_p9_tm_emulation()
205 		vcpu->arch.shregs.msr &= ~MSR_TS_MASK;  in kvmhv_p9_tm_emulation()
206 		vcpu->arch.regs.nip += 4;  in kvmhv_p9_tm_emulation()
213 		if (!(vcpu->arch.hfscr & HFSCR_TM)) {  in kvmhv_p9_tm_emulation()
214 			vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
215 			vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;  in kvmhv_p9_tm_emulation()
216 			vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;  in kvmhv_p9_tm_emulation()
221 			vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;  in kvmhv_p9_tm_emulation()
222 			vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;  in kvmhv_p9_tm_emulation()
228 		if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {  in kvmhv_p9_tm_emulation()
236 		vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |  in kvmhv_p9_tm_emulation()
238 		vcpu->arch.shregs.msr = msr | MSR_TS_S;  in kvmhv_p9_tm_emulation()
239 		vcpu->arch.regs.nip += 4;  in kvmhv_p9_tm_emulation()