Lines Matching +full:wdt +full:- +full:interval
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
8 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1998-1999 TiVo, Inc.
39 #include <asm/asm-offsets.h>
48 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
49 * r4 - Starting address of the init RAM disk
50 * r5 - Ending address of the init RAM disk
51 * r6 - Start of kernel command line string (e.g. "mem=96m")
52 * r7 - End of kernel command line string
54 * This is all going to change RSN when we add bi_recs....... -- Dan
123 lis r11,(critirq_ctx-PAGE_OFFSET)@ha
124 lwz r11,(critirq_ctx-PAGE_OFFSET)@l(r11)
128 lwz r11,TASK_STACK-THREAD(r11) /* this thread's kernel stack */
130 addi r1,r11,THREAD_SIZE-INT_FRAME_SIZE /* Alloc an excpt frm */
131 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)) /* re-enable MMU */
176 * r0, r3-r8 saved in stack frame
190 * 0x0100 - Critical Interrupt Exception
195 * 0x0200 - Machine Check Exception
200 * 0x0300 - Data Storage Exception
213 * 0x0400 - Instruction Storage Exception
214 * This is caused by a fetch from non-execute or guarded pages.
225 /* 0x0500 - External Interrupt Exception */
228 /* 0x0600 - Alignment Exception */
236 /* 0x0700 - Program Exception */
249 /* 0x0C00 - System Call Exception */
258 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
262 /* 0x1010 - Fixed Interval Timer (FIT) Exception */
266 /* 0x1020 - Watchdog Timer (WDT) Exception */
270 /* 0x1100 - Data TLB Miss Exception
331 2: /* Check for possible large-page pmd entry */
344 /* The bailout. Restore registers to pre-exception conditions
355 /* 0x1200 - Instruction TLB Miss Exception
415 2: /* Check for possible large-page pmd entry */
428 /* The bailout. Restore registers to pre-exception conditions
462 * The exception handler was handling a non-critical interrupt, so it will
466 /* 0x2000 - Debug Exception */
471 * If this is a single step or branch-taken exception in an
478 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
514 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
524 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
532 /* Watchdog Timer (WDT) Exception. (from 0x1020) */
540 /* Other PowerPC processors, namely those derived from the 6xx-series
542 * However, for the 4xx-series processors these are neither defined nor
548 * exception space :-). Both the instruction and data TLB
550 * r10 - TLB_TAG value
551 * r11 - Linux PTE
552 * r9 - available to use
553 * PID - loaded with proper value when we get here
562 * Clear out the software-only bits in the PTE to generate the
572 andi. r9, r9, PPC40X_TLB_SIZE - 1
606 stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1)
680 iccci r0,r3 /* Invalidate the i-cache before use */
710 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */