Lines Matching +full:use +full:- +full:push +full:- +full:pull
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Each interrupt source has a 2-bit state machine called ESB
21 * needs to be re-triggered.
24 * manipulate the PQ bits. They must be used with an 8-bytes
41 * Load-after-store ordering
44 * load-after-store ordering. This is required to use StoreEOI.
46 #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
63 #define TM_NSR 0x0 /* + + - + */
64 #define TM_CPPR 0x1 /* - + - + */
65 #define TM_IPB 0x2 /* - + + + */
66 #define TM_LSMFB 0x3 /* - + + + */
67 #define TM_ACK_CNT 0x4 /* - + - - */
68 #define TM_INC 0x5 /* - + - + */
69 #define TM_AGE 0x6 /* - + - + */
70 #define TM_PIPR 0x7 /* - + - + */
99 * - Byte load from QW0[NSR] - User level NSR (EBB)
100 * - Byte store to QW0[NSR] - User level NSR (EBB)
101 * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
102 * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
104 * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
111 #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
112 #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */
114 #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */
115 #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/
117 #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */