Lines Matching +full:0 +full:x05000000
29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
47 #define LCTRL2_LW0EN 0x80000000
48 #define LCTRL2_LW0LA_E 0x00000000
49 #define LCTRL2_LW0LA_F 0x04000000
50 #define LCTRL2_LW0LA_EandF 0x08000000
51 #define LCTRL2_LW0LADC 0x02000000
52 #define LCTRL2_SLW0EN 0x00000002
60 #define IDC_ENABLE 0x02000000 /* Cache enable */
61 #define IDC_DISABLE 0x04000000 /* Cache disable */
62 #define IDC_LDLCK 0x06000000 /* Load and lock */
63 #define IDC_UNLINE 0x08000000 /* Unlock line */
64 #define IDC_UNALL 0x0a000000 /* Unlock all */
65 #define IDC_INVALL 0x0c000000 /* Invalidate all */
67 #define DC_FLINE 0x0e000000 /* Flush data cache line */
68 #define DC_SFWT 0x01000000 /* Set forced writethrough mode */
69 #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
70 #define DC_SLES 0x05000000 /* Set little endian swap mode */
71 #define DC_CLES 0x07000000 /* Clear little endian swap mode */
75 #define IDC_ENABLED 0x80000000 /* Cache is enabled */
76 #define IDC_CERR1 0x00200000 /* Cache error 1 */
77 #define IDC_CERR2 0x00100000 /* Cache error 2 */
78 #define IDC_CERR3 0x00080000 /* Cache error 3 */
80 #define DC_DFWT 0x40000000 /* Data cache is forced write through */
81 #define DC_LES 0x20000000 /* Caches are little endian mode */