Lines Matching +full:interrupt +full:- +full:ranges
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 reset-type = <2>; /* Use chip-reset */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440spe","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-440spe","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-440spe","ibm,uic";
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
83 interrupt-parent = <&UIC0>;
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-440spe","ibm,uic";
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
95 interrupt-parent = <&UIC0>;
99 compatible = "ibm,sdr-440spe";
100 dcr-reg = <0x00e 0x002>;
104 compatible = "ibm,cpr-440spe";
105 dcr-reg = <0x00c 0x002>;
109 compatible = "ibm,mq-440spe";
110 dcr-reg = <0x040 0x020>;
114 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
115 #address-cells = <2>;
116 #size-cells = <1>;
117 /* addr-child addr-parent size */
118 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
128 clock-frequency = <0>; /* Filled in by U-Boot */
131 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
132 dcr-reg = <0x010 0x002>;
136 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
137 dcr-reg = <0x180 0x062>;
138 num-tx-chans = <2>;
139 num-rx-chans = <1>;
140 interrupt-parent = <&MAL0>;
142 #interrupt-cells = <1>;
143 #address-cells = <0>;
144 #size-cells = <0>;
145 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
153 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
157 clock-frequency = <0>; /* Filled in by U-Boot */
160 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
161 dcr-reg = <0x012 0x002>;
162 #address-cells = <2>;
163 #size-cells = <1>;
164 clock-frequency = <0>; /* Filled in by U-Boot */
165 /* ranges property is supplied by U-Boot */
167 interrupt-parent = <&UIC1>;
170 compatible = "cfi-flash";
171 bank-width = <2>;
173 #address-cells = <1>;
174 #size-cells = <1>;
196 label = "u-boot";
206 virtual-reg = <0xa0000200>;
207 clock-frequency = <0>; /* Filled in by U-Boot */
208 current-speed = <115200>;
209 interrupt-parent = <&UIC0>;
217 virtual-reg = <0xa0000300>;
218 clock-frequency = <0>;
219 current-speed = <0>;
220 interrupt-parent = <&UIC0>;
229 virtual-reg = <0xa0000600>;
230 clock-frequency = <0>;
231 current-speed = <0>;
232 interrupt-parent = <&UIC1>;
237 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
239 interrupt-parent = <&UIC0>;
244 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
246 interrupt-parent = <&UIC0>;
248 #address-cells = <1>;
249 #size-cells = <0>;
258 linux,network-index = <0x0>;
260 compatible = "ibm,emac-440spe", "ibm,emac4";
261 interrupt-parent = <&UIC1>;
264 local-mac-address = [000000000000];
265 mal-device = <&MAL0>;
266 mal-tx-channel = <0>;
267 mal-rx-channel = <0>;
268 cell-index = <0>;
269 max-frame-size = <9000>;
270 rx-fifo-size = <4096>;
271 tx-fifo-size = <2048>;
272 phy-mode = "gmii";
273 phy-map = <0x00000000>;
274 has-inverted-stacr-oc;
275 has-new-stacr-staopc;
281 #interrupt-cells = <1>;
282 #size-cells = <2>;
283 #address-cells = <3>;
284 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
286 large-inbound-windows;
287 enable-msi-hole;
294 /* Outbound ranges, one memory and one IO,
297 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
301 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
304 bus-range = <0x0 0xf>;
306 /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
307 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
308 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
313 #interrupt-cells = <1>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
321 dcr-reg = <0x100 0x020>;
322 sdr-base = <0x300>;
324 /* Outbound ranges, one memory and one IO,
327 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
331 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
334 bus-range = <0x10 0x1f>;
338 * We are de-swizzling here because the numbers are actually for
341 * below are basically de-swizzled numbers.
344 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
345 interrupt-map = <
354 #interrupt-cells = <1>;
355 #size-cells = <2>;
356 #address-cells = <3>;
357 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
362 dcr-reg = <0x120 0x020>;
363 sdr-base = <0x340>;
365 /* Outbound ranges, one memory and one IO,
368 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
372 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
375 bus-range = <0x20 0x2f>;
379 * We are de-swizzling here because the numbers are actually for
382 * below are basically de-swizzled numbers.
385 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
386 interrupt-map = <
394 compatible = "ibm,i2o-440spe";
396 dcr-reg = <0x060 0x020>;
400 compatible = "ibm,dma-440spe";
401 cell-index = <0>;
403 dcr-reg = <0x060 0x020>;
404 interrupt-parent = <&DMA0>;
406 #interrupt-cells = <1>;
407 #address-cells = <0>;
408 #size-cells = <0>;
409 interrupt-map = <
415 compatible = "ibm,dma-440spe";
416 cell-index = <1>;
418 dcr-reg = <0x060 0x020>;
419 interrupt-parent = <&DMA1>;
421 #interrupt-cells = <1>;
422 #address-cells = <0>;
423 #size-cells = <0>;
424 interrupt-map = <
429 xor-accel@400200000 {
430 compatible = "amcc,xor-accelerator";
432 interrupt-parent = <&UIC1>;
438 stdout-path = "/plb/opb/serial@f0000200";